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A Brief Overview of Failure Mechanism Models

Posted by Ed Wyrwas on Apr 6, 2016 11:01:25 AM

Charting_Failures.jpgThe most prevalent and commonly simulated failure mechanisms in Si-based microelectronic devices are Electromigration (EM), Time Dependent Dielectric Breakdown (TDDB), Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI).

These mechanisms can be generally categorized as Steady State Failure Modes (EM and TDDB) and Wearout Failure Modes (NBTI and HCI). Steady State Failure Modes are typically random cases of “stress exceeding strength.” The hazard functions generated by random failure modes are constant over time and may produce failures during all bathtub curve stages. Conversely, Wearout Failure Modes generate increasing hazard function and are predominate in later stages of the device life. Wearout Failure Modes at sub-micron nodes are experienced earlier in the anticipated life of a device, within the range once considered dominated only by the Steady State Failure Modes.

There are a number of failure mechanisms that contribute to the overall device failure rate:

Electromigration (EM) can lead to interconnect failure in an integrated circuit. It is characterized by the migration of metal atoms in a conductor along the direction of the electron flow. EM causes opens or voids in some portions of the conductor and corresponding hillocks in other portions.

Time Dependent Dielectric Breakdown (TDDB) is caused by defect generation and accumulation that reaches a critical density in the oxide film. 

Negative Bias Temperature Instability (NBTI) occurs only in pMOS devices stressed with a negative gate bias voltage while at elevated temperatures. Degradation occurs in the gate oxide region allowing electrons and holes to become trapped.

Hot Carrier Injection (HCI) occurs in both nMOS and pMOS devices stressed with drain bias voltages. High electric fields energize the carriers (electrons or holes), which are then injected into the gate oxide region. Like NBTI, the degraded gate dielectric can then more readily trap electrons or holes.

Simulating these types of failure mechanisms can be time consuming and challenging, which is why we developed Sherlock Automated Design Analysis™ Software. Unlike any other product on the market, Sherlock uses the same actual design files to model and simulate the electronics for Physics of Failure testing and analysis. The automated process accurately predicts reliability and improves product performance using real world applications, allowing engineers to focus on enhancing products and eliminating inefficient rework and costly testing cycles.

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Effective Reliability Test Plan Development Using Physics of Failure