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Challenges with Package on Package (PoP): Part 1, Manufacturability

Posted by Craig Hillman, Cheryl Tulkoff and Greg Caswel on Jul 25, 2016 4:15:24 PM

The future of electronic package is 3D. From stacked die to Intel’s recent introduction of the 3D transistor1, the continued progression in Moore’s Law is being accomplished by going ‘up’. For the majority of design engineers, nowhere is this trend more concrete then the increasing utilization of components offered with a package-on-package (PoP) architecture.

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Topics: electronic package, Stencil Design, NSMD

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