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Predicting the Reliability of Zero-Level TSVs

Posted by Greg Caswell and Craig Hillman on Aug 23, 2016 10:54:45 AM

Semiconductor integration has continued for several years in the electronics industry, essentially in a two- dimensional approach. This continuing reduction in gate geometries and packaging has resulted in a drive toward interconnection of dies in a 3D approach without increasing power, by utilizing connections through the silicon itself. This process of interconnection, called through-silicon-vias (TSVs), provides a means of connecting signal paths from the top of a die to the bottom for easier, faster die to die signal propagation by utilizing the area under the bond pads. Vertical chip stacking in a single package increases the amount of silicon that can be put into a given package footprint. Stacking die also provides a faster signal path as a result of the shorter die to die routing and reduces the number of placements for board assembly by reducing the number of components. Connecting devices in a 3D approach promises higher clock rates, lower power dissipation, and higher integration density.(2) However, many of these new technologies are implemented before the reliability of the technology is full understood.

This paper will address some of the failure modes that occur with TSV’s and the resultant impact on reliability.

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Topics: TSVs, semiconductor integration, reliability

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