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• Controller Section: Model TC10
• Temperature Setpoint Range: -73°C to +315°C in 0.1°C steps (LN2 option; -183°C to +315°C)
• Time at Temperature Range: 1.0 sec to 99 hrs 59 min 59 sec or continuous
• Temperature Ramping Rate Control: Locally controlled from 0.01°C/min up to the specified heat/cool rate of change
• Programmable Set Temps and Times: Number of set temperatures and times limited only by available program memory — typically 100+ segments
• Absolute Error (not including probe error): +/- 0.25°C
• Long Term Stability (per month): +/- 0.2°C
• Temperature Resolution: 0.02°C
• Line Voltage Sensitivity (105-125 VAC): +/- 0.1°C
• Programmable Temperature Loop Control: 1 to 65535 FOR/NEXT loop executions for 10 loops, nesting supported
• Temperature Control Technique: PID algorithm/pulse width modulated, programmable from keyboard or remote interfaces
• Option to control to chamber probe or user probe
• Local Operation: 26-key keypad/2-line LCD display
• Remote Operation: Built-in IEEE-488/RS232/RS422 interfaces

JESD22-A100-B (revision of JESD22-A100-A)

Cycled Temperature-Humidity-Bias Life Test

Objective

To assess the reliability of non-hermetically packaged solid state devices. By power biasing the devices in an environment with extreme field temperatures and humidity levels, the device lifetime can be accelerated to failure.

Test Conditions

• Test Duration: 1008 (-24, +168) hours
• Biasing:
  • Continuous voltage bias applied: For optimal biasing conditions, the temperature of die must be less than or equal to an upper temperature limit given by “the chamber temperature +10°C.”
  • Cycled voltage bias applied: A cycled power bias with a one-hour-on/one-hour-off duty cycle is optimal for various plastic encapsulated microcircuits. A cycled bias allows for the sufficient deposition of moisture.
• Temperature-Humidity-Bias testing
• Failure is when parametric limits are exceeded or when functionality cannot be demonstrated under nominal or worst-case conditions, per designer’s specifications.

Samples

Non-hermetic plastic encapsulated integrated chips