Electric vehicles are practically computers on wheels. New innovations such as active and passive safety systems, electric propulsion, and semi and fully autonomous vehicles have all contributed to an increase in the usage of electronics in automotive applications. More importantly, automotive designers must still adhere to the same size and packaging constraints to ensure vehicles’ size and weight does not increase. To resolve this dilemma, automotive designers often rely on components being tightly placed on both sides of the Printed Circuit Board (PCB) to ensure the most efficient use of board space.
Industry interest in producing thinner and smaller integrated circuit (IC) packages to match the performance of chip scale packages has resulted in the wide application of quad flat no-lead (QFN) components. However, the small-form factor of QFN packages can place solder joints at risk of coefficient of thermal expansion (CTE) mismatch, which can potentially lead to PCB warping and failure. To help mitigate this risk and accurately assess the fatigue life of solder interconnects in QFN packages, a predictive model incorporating the material and geometric parameters that influence solder joint fatigue should be used.