For semiconductor manufacturers entering the automotive environment, the lack of universal qualifications standards often leads to inconsistent reliability expectations. To be successful in the competitive landscape, semiconductor manufacturers must account for differences in how automotive OEMs and their suppliers qualify integrated circuits compared to consumer products. A key factor in the qualification process is the critical importance of board level reliability testing. Given the varied requirements and absence of mutually agreed standards, semiconductor manufacturers often struggle to develop a relevant and successful board level reliability test plan.
DEVELOPING A BOARD LEVEL RELIABILITY TEST (BLRT) PLAN
The first step in developing a BLRT plan is identifying which tests will be part of it. By far the most important test to include in BLRT is temperature cycling. Performing temperature cycling as part of every BLRT plan is critical because:
- It is the second most common environment across potential customers, after constant temperature. Far fewer customers experience excessive humidity, vibration, or mechanical shock.
- It is the stress most likely to cause failure of BGA and QFN solder joints.
- It is the longest and most expensive qualification test performed by Tier 1 and OEMs.
- There have been several industry-wide issues regarding package failures that only occur when temperature cycling assembled parts. These issues include copper wire bond failures and low-K dielectric cracking (also known as chip-package-board interaction [CPBI]).
Choosing a specific standard for temperature cycling, whether JESD22A105 or IPC-9701, is not critical (unless a big customer requires it!). The most important aspects are selecting the minimum temperature, the maximum temperature, the number of temperature cycles, and the test coupon design. Common mistakes in picking these test parameters include:
- Assuming the minimum and maximum test temperature should be the same as the minimum and maximum rated temperature
- Choosing something other than 1000 cycles (test cycles other than 1000 can make customers nervous)
- Failing to take full advantage of the test coupon design to reduce risk, pass BLRT, and streamline customer acceptance
Other potential BLR tests, such as power cycling, temperature/humidity, mechanical shock, vibration, and bend testing, depend on finding the appropriate balance between industry standards (relatively few), customer requirements (difficult if you have 10,000 customers), and ability to pass the test (something that should be evaluated before BLRT).
BLRT RISK ASSESSMENT
Because BLRT can be expensive and time consuming, it is important to have performed a robust risk assessment before physical testing to have high confidence in BLRT success. But this can be challenging, if not impossible, for most semiconductor manufacturers because of the methods that are currently used to perform risk assessments. Specifically, most semiconductor manufacturers and their OSAT vendors use either overly complex three-dimensional (3D) finite element analysis (FEA) or overly simplistic reliability by similarity (RBS).
The use of 3D FEA within semiconductor manufacturers and OSATs has become increasingly important with the rise of more complex semiconductor packaging (‘More than Moore’), including stacked die, system-in-package, and through-silicon via. For a successful launch of a 3D package, the industry needs to accurately capture electrical and thermal stresses and how they are influenced by die-package interaction. However, performing 3D FEA is time-consuming and requires highly specialized experts. Semiconductor manufacturers typically only use 3D FEA on BLR risk assessment for a very small subset of devices because 3D FEA cannot be used by the design team. These specialized experts use 3D FEA throughout the new product development process, most often in either high-profile programs or baseline programs in which multiple derivatives are spun off.
For all other programs, semiconductor manufacturers try to rely on reliability by similarity (that is, is the new device sufficiently similar enough to a device that passed BLR so that we can assume it will also pass BLR?). The danger, of course, is this technique relies on human judgement and questionable assumptions. Assumptions that can be very expensive when the device fails BLR.
Given the limitations of both techniques, several semiconductor manufacturers have started to transition to a third approach. This technique involves using reliability physics-based closed-form equations, such as the Blattau Model, that can either allow design teams to perform a BLR risk assessment on their own or allows the analyst teams to more rapidly extrapolate existing 3D FEA results to a wider range of devices
BLRT COUPON DESIGN
One of the most unappreciated aspects of a successful BLRT (for both the device manufacturer and its customers) is the design of the test coupon. The coupon thickness, coupon materials, coupon stackup, bond pad design, and how the coupon is constrained can all play critical roles in passing BLRT while also being relevant to the most important customers. One classic example of this conundrum is the presence or absence of microvias under the BGA pad.
Once the solder ball pitch under a ball grid array (BGA) drops to 0.5mm or below, almost all board-level designs require the use of microvias. While some designs can get away with a single layer of microvias, it is very common to have two or even three layers of microvias stacked on top of each other. These microvias can create an anchor to the solder ball, increasing the stiffness and greatly reducing the time to failure. However, most BLRT coupons have no microvias, much less a triple-stack. The result is devices passing JEDEC-style BLRT while failing Tier 1 or OEM qualification activities.
TEST SETUP FOR BLRT IS NOT TURNKEY
Finally, once all the test parameters have been selected and success has been confirmed, it is time to perform BLRT. However, testing is not as turnkey as one would expect. Despite designing a unique and specific test flow, other factors arise that require additional adjustments. Calibration approaches for attachment, monitoring techniques, monitoring frequency, temperature control across the chamber and failure definition are all critical for test relevance, test repeatability, and acceptance by the broader industry. Furthermore, those factors are changing and developing at a rapid pace. This is where expansive industry BLRT experience and involvement is crucial to success.
Design teams already bear immense responsibilities during the design process, which does not afford them the time or opportunity to continually refresh BLR testing standards. The key to implementing an efficient BLRT plan is operational intelligence on the expectations of OEMs, suppliers and manufacturers across the industry to create a two-way street of information. This industry knowledge creates an expedited process for renewing testing standards at a pace that is consistent with speed of change and disruption. Keeping pace is a critical factor for implementing a fluid and ubiquitous testing plan that is repeatable.
BLRT should be tailored to apply to individual cases, rather than a general threshold. As the applications of semiconductor products diversify, the stresses they experience become increasingly vast. Because use environments are expanding rapidly, frequent and accurate testing with agreed upon expectations is essential for reliability success. However, goals are not always universally aligned throughout the supply chain. Considering OEMs, suppliers, and manufacturers can often have differing needs and priorities, an outside consultant specializing in BLRT can expedite time-to-market and cut costs given their understanding of the goals of each party involved.
Contact a DfR Solutions representative today to learn more about the turnkey implementation and execution of a BLRT plan in which manufacturers can have a high degree of confidence.