While amazingly powerful thermal tools can predict the distribution of junction, case and ambient temperatures in minute detail, it is often difficult to know what the temperatures should be instead of knowing what the temperatures will be. Even derating, the straightforward and long-held industry go-to methodology, cannot answer the “How hot is too hot?” question.
Using thermal tool guestimates is not a viable way to protect integrated circuits and solder joints against temperature-related failure. A more efficient approach is one that uses reliability physics to interpret thermal modeling and measurement data.
Integrated Circuit Wearout
Submicron process technologies can drive integrated circuit (IC) wearout well before a device reaches the end of its anticipated lifetime, making it necessary to investigate the effects of use and environmental conditions on IC components.
Microprocessor and microcontroller development has generally followed Moore’s Law of doubling the number of transistors on a die approximately every two years. As a result, reduction in transistor sizes create faster, smaller ICs with greatly reduced power dissipation – at the expense of introducing an underlying reliability risk.
Semiconductor failure mechanisms in feature sizes measuring in the tens of nanometers result in shorter device lifetimes and unanticipated early device wearout, principally due to increased thermal stresses. Four failure mechanisms, each with a unique combination of temperature, voltage, current and frequency, drive this issue:
- Electromigration (EM)
- Time Dependent Dielectric Breakdown (TDDB)
- Hot Carrier Injection (HCI)
- Negative Bias Temperature Instability (NBTI)
Solder Joint Fatigue
Solder joints provide electrical, thermal and mechanical connections between electronic components and the substrate or board to which it is attached. Their function is imperative for board success.
Subjecting solder joints to temperature fluctuations can result in joint stress and fatigue. The components and printed board will expand or contract by dissimilar amounts due to differences in the coefficient of thermal expansion (CTE). Repeated exposure to temperature changes leads to accumulated damage within the solder joint, leading to crack propagation and eventual failure.
Failure of solder joints due to thermo-mechanical fatigue is one of the primary wearout mechanisms in electronic products. Inappropriate design, material selection and use environments can result in relatively short times to failure.
Thermo-mechanical solder joint fatigue is influenced by:
- Maximum temperature
- Minimum temperature
- Dwell time at maximum temperature
- Component design (i.e., size, number of I/O)
- Component material properties (i.e., CTE, elastic modulus)
- Solder joint geometry
- Solder joint material (i.e., SnPb, SAC305)
- Printed board thickness
- Printed board in-plane material properties (i.e., CTE, elastic modulus)
The ability to analyze and understand the impact that thermal effects have on failure mechanisms and device reliability is necessary to mitigate failure risk and guarantee reliable products. A combination of Physics of Failure (PoF), semiconductor formulae and industry-accepted mechanism models best predicts component reliability.
Sherlock Automated Design Analysis™ Software uses PoF to identify when thermal temperatures are too hot for integrated circuits and solder joints, and find solutions based on real-life data inputs and complex calculations performed in comprehensive software databases. This allows engineers to quickly course correct in the design stage, saving time and money while ensuring products will consistently pass testing on the first round.
Find out more about reliability physics in our whitepaper, Thermal Management: How Hot is Too Hot? Click the button below to download your free copy now.