Product test plans are critical to the success of a new product or technology. Preparing a viable test plan involves several steps to properly identify the requirements for the tests. While many test parameters will vary from product to product, there are elements of the methodology for a test plan approach that remain consistent. These include the necessity for a BOM review to determine part limitations, assessing the field environmental conditions so they can be properly mapped to the tests implemented, and the impact of failure history, should it exist. The objective is to develop a test plan that does not stress the assembly to a level where a failure might not be experienced in the field.
As the smartphone market has stagnated, semiconductor manufacturers have started to pivot their focus to automotive electronics to find the next large volume growth opportunity. This adjustment is for good reason: while smartphone volumes have not changed in over three years, automotive electronics will be the fastest growing market for integrated circuits until at least 2021.
To be successful in the competitive landscape that is automotive electronics, semiconductor manufacturers must account for differences in how automotive OEMs and their suppliers qualify integrated circuits compared to consumer products. While the differences are numerous, a key factor is the critical importance of board level reliability testing.
For semiconductor manufacturers entering the automotive environment, the lack of universal qualifications standards often leads to inconsistent reliability expectations. To be successful in the competitive landscape, semiconductor manufacturers must account for differences in how automotive OEMs and their suppliers qualify integrated circuits compared to consumer products. A key factor in the qualification process is the critical importance of board level reliability testing. Given the varied requirements and absence of mutually agreed standards, semiconductor manufacturers often struggle to develop a relevant and successful board level reliability test plan.