Plated through holes (PTH) and vias are structures that interconnect signal circuits at different PCB layers. They are typically categorized as through vias (or PTH), blind vias, and buried vias. Due to the higher I/O density and smaller electronic packages evolving in the past decades, the demand for high density interconnects has increased significantly.
Microvias can be stacked or staggered (Figure 1.) depending on their placement throughout different copper layers. Both stacked and staggered microvias offer increased reliability in comparison to traditional PTHs, and staggered microvias have shown to be more reliable than stacked microvias. Even with the increased robustness of staggered microvias, PTHs and vias in general are the most common causes of open circuits in PCBs.
The complications involved with mapping out vias and PTHs make them an area of high concern across the electronics industry when it comes to reliability. Developing models that can predict the reliability and manufacturability of the interconnects is challenging because there is a lack of detailed characterization of the materials frequently involved in the use of vias and PTHS.
In this article, we introduce a method for simulating based of off FEA results to analyze the reliability of PCBs that utilize microvias or PTHs and explain how the method was validated against experimental results. Then, the article explains how manufacturing analyses provided the insight required to set reliability goals for microvias and PTHs.
Ensuring the reliability of PCBs that are utilizing microvias and plated through holes can present significant concerns. A major reliability challenge stems from microvias and PTHs often featuring copper coating. A Coefficient of Thermal Expansion mismatch between the copper in the microvias and PTHs and the PCB material is the most frequent source of failure in PTHs and vias (Figure 2.).
Figure 2. Ji, Li-Na, Yi Gong, and Zhen-Guo Yang. 2010. “Failure Investigation on Copper-Plated Blind Vias in PCB.” Microelectronics Reliability 50 (January): 1163–70
To address this failure mechanism, reliability engineers can use FEA results to predict cycles to failure due to fatigue. More specifically, for every element along the z-axis (out of plane) of a PCB, the equivalent plastic strain can be averaged for all the elements across the barrel thickness of the PTH. The next step is to compute the strain increment for the set of elements with maximum averaged equivalent plastic. With the strain values in hand, the Coffin-Manson equation estimates the number of cycles to failure.
After developing a method for addressing the reliability challenges inherent in the use of mircovias using FEA results, we sought extensive validation using multiple experimental results to find out whether they correlated with the predictions made from FEA results.
Figure 3. The image below depicts the development of a contour of equivalent plastic strain in a typical PTH featuring a 12-layer board under thermal cyclic loading of 25°C to 150°C.
One of the main challenges in experimental works related to electronics industry and reliability analysis is to perform accurate statistical analysis considering the long daisy chains being used. This implies that the number of suspensions is as important as the failures in doing statistical analysis. The simulation and modeling analysis relied on the cycle to first failure without any suspensions for the statistical analysis. Considering suspended data points, the results provided a more accurate and appropriate analysis. In the end, the model prediction utilizing FEA results for all PTH configurations strongly correlated with experimental results.
Once we validated the method for analyzing microvias and PTHs based off FEA results, the next step was to perform manufacturability analyses to achieve the ultimate goal of successfully predicting cycles to failure due to fatigue.
Manufacturability analyses for stacked and single microvias were completed to predict the likelihood of interfacial separation during the reflow process. The interfacial separation between microvia bodies and target/capture pad occur due to tensile overstress during solder reflow. Based on experimental results and copper properties, the following stress ranges were identified:
- σ22 < 120MPa Pass
- 120MPa ≤ σ22 < 160MPa ) Need attention
- 160 MPa ≤ σ22 ) Failure
In theory, microvia structures are designed to withstand stress levels up to copper’s ultimate strength stress values (σuts). However, due to the manufacturing defects and presence of electroless copper in the microvia bodytarget/capture pad interfaces, microvias fail at much lower stress levels. After completing a comprehensive literature review and evaluating accepted industry knowledge, an empirical critical stress value of 0.65 σuts was used as a failure indicator. Considering that information, since σuts of copper is about σuts = 250 MPa, the critical value of 160 MPa is chosen for a failure indication.
With the insights from the experiment providing the critical information that a value of 160MPa indicates failure has occurred, ANSYS developed a fully automated technique for ANSYS Sherlock Automated Design Analysis to analyze a PCB design with thousands of interconnect structures and predict the probability of failure due to overstress and fatigue conditions. This gives ANSYS Sherlock users the tools necessary to identify reliability concerns when developing PCBs featuring microvias and PTHs, such as how the CTE mismatch between a copper-plated interconnect and PCB material will affect a product over its entire lifecycle. After identifying areas of concern, designers can address those challenges proactively before sinking resources into a prototype.