Eutectic AuSn solder is increasingly used in high reliability and/or high temperature applications where conventional SnPb and Pb-free solders exhibit insufficient strength, creep resistance, and other issues. These applications include hybrid microelectronics (particularly flip chips), MEMS, optical switches, LEDs, laser diodes, RF devices, and hermetic packaging for commercial, industrial, military, and telecommunications applications. For most of these applications, AuSn provides the additional benefit of not requiring flux during reflow, significantly reducing the potential for contamination and pad corrosion. However, the materials and processing considerations are substantially different than for conventional solders. Many companies struggle with issues such as poor solder flow, excessive void formation, variable reflow temperature (arising from off-eutectic compositions), heterogeneous phase distribution, and others, all contributing to development delays, process yield loss, and field reliability issues. This paper reviews the critical issues in material and process selection, as well as long term diffusion and mechanical stability.
Those who interact closely with DfR realize that we proscribe to the theory of the ‘reliability cycle’. The early years of electronics, 1950’s and 1960’s, were disasters for reliability and led to the establishment of the organizations and tools currently used today (IRPS, MEOST, RAMS, FMEA, etc.). Establishment of large electronic OEMs such as Motorola, Texas Instruments, and IBM in 1970’s and early 1980’s resulted in extensive reliability practices and organizations that are still awe-inspiring, even today.
The breakup of these organizations and the dominance of cheap consumer electronics in the early 1980’s through the mid 1990’s brought on electronics that would fail if you breathed on it too hard. Realizing that some degree of reliability was required and faced with the great uncertainties of environmental legislation, international OEMs brought new tools and new resources that rivaled the activities of their peers 25 years ago, but without the excessive costs that killed market share (think planned obsolescence: it just needs to be reliable enough). Certain electronic OEMs quadrupled their reliability staffs in a matter of few years.
emiconductor technology advances have been fulfilling Moore’s law for many decades. However, with feature sizes approaching atomic dimensions, alternative technologies will be needed to meet the evolving performance, size and cost demands driven by applications from mobile to cloud computing. One example of such technologies is heterogeneous semiconductor packaging technology such as 3D packaging.
This is the first of a series of perspectives on common, but avoidable, problems that I have encountered in the development and qualification of components for use in high reliability opto-electronic applications. Some of these problems may appear intuitive, and therefore absurd, to engineers with specific academic or established telecom OEM backgrounds, where projects run for many years and are supported by significant past experience and/or applied research. However, the proliferation of start-ups, radical shortening of development cycles, general dilution of knowledgeable engineers (both in vendors’ product development and customers’ reliability assessment groups), constant cost reduction pressure from customers, and outsourcing/offshore production have all colluded to promote quick, ill-informed design and process decisions. One of the key value propositions of DfR Solutions is to provide guidance during the design and development phases, in order to avoid expensive and reputation-damaging mistakes in the future.
Myth 1: I don’t worry about design, because most of my problems are with defects from suppliers
While the majority of product failure can be traced back to supplier or manufacturing issues, the most severe warranty issues tend to be design-related, because every product at every customer can be at risk. As a result, design issues are much more likely to result in a recall and therefore place a much larger strain on a company’s bottom line.
Component obsolescence management is a strategic practice that also mitigates the risk of counterfeit parts. Left unchecked, obsolescence issues increase support, development and production costs. So, planning ahead is critical. For companies that do proactively manage component availability and obsolescence, the effect of long-term storage on manufacturability and reliability is the area of major concern. Many issues can arise depending on the component technology and storage environment. Reliability concerns to consider include solderability, stress driven diffusive voiding, moisture, Kirkendall voiding, intermetallics/oxidation and tin whiskering.
When component obsolescence isn’t planned for, the secondary market is often the supply chain of last recourse. While it is possible to get high quality, genuine parts, it is also possible to get nonconforming, reworked, or counterfeit components. And, it is increasingly difficult to differentiate genuine parts from their counterfeit equivalents. Historically, the secondary market provided a mechanism for finding parts in short supply or at reduced cost. Today, high-reliability system manufacturers are less willing to risk contamination of their supply chain with potentially substandard parts in order to save a few dollars on the cost of a part.
This paper will cover obsolescence management strategies, relevant industry standards, use of managed supply programs (MSP) and contract pooled options, plus long term storage recommendations and practices.
Semiconductor integration has continued for several years in the electronics industry, essentially in a two- dimensional approach. This continuing reduction in gate geometries and packaging has resulted in a drive toward interconnection of dies in a 3D approach without increasing power, by utilizing connections through the silicon itself. This process of interconnection, called through-silicon-vias (TSVs), provides a means of connecting signal paths from the top of a die to the bottom for easier, faster die to die signal propagation by utilizing the area under the bond pads. Vertical chip stacking in a single package increases the amount of silicon that can be put into a given package footprint. Stacking die also provides a faster signal path as a result of the shorter die to die routing and reduces the number of placements for board assembly by reducing the number of components. Connecting devices in a 3D approach promises higher clock rates, lower power dissipation, and higher integration density.(2) However, many of these new technologies are implemented before the reliability of the technology is full understood.
This paper will address some of the failure modes that occur with TSV’s and the resultant impact on reliability.
The majority of electronic failures occur due to thermally induced stresses and strains caused by excessive differences in coefficients of thermal expansion (CTE) across materials.
CTE mismatches occur in both 1st and 2nd level interconnects in electronics assemblies. 1st level interconnects connect the die to a substrate. This substrate can be underfilled so there are both global and local CTE mismatches to consider. 2nd level interconnects connect the substrate, or package, to the printed circuitboard (PCB).This would be considered a “boardlevel” CTE mismatch.Severa lstress and strain mitigation techniques exist including the use of conformal coating.
Reliability models, based on physics-of-failure mechanisms, have been developed for dynamic random access memories (DRAM), microcontrollers and microprocessors using a new software tool. Field data from a large fleet of mobile communications products, that were deployed over a period of 8 years, were analyzed to validate the tool’s accuracy. Strong correlation of 80% is demonstrated between measured and predicted values.
Qualification of new technologies, new vendors, or new manufacturing locations is one of the most challenging issues for OEMs and component manufacturers. It is particularly problematic for opto-electronic devices, given their lower manufacturing maturity with respect to micro-electronics and typically more stringent reliability requirements. Furthermore, many OEMs and component manufacturers are reducing reliability staffing & capabilities to decrease costs, such that fewer engineers are forced to evaluate an ever wider array of technologies and suppliers. DfR Solutions can provide assistance to our customers in three key ways: Destructive physical analysis, On-site vendor reliability audits, Review of qualification, failure analysis, and corrective action reports
This white paper provides an overview of our services in each of the three areas.