DfR Solutions Reliability Designed and Delivered

Discussion on Cracking/Separation in Filled Vias

Nathan Blattau, PhD

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The Knadle “PTH life curve" has been used for over 15 years to characterize new materials or PTH structures, and to calculate via life for any combination of temperatures. Error! Reference source not found. depicts these life curves to review the problem that drives all others—the CTE mismatch between the copper barrel and the laminate at reflow temperatures.    This mismatch can produce deformations such that that even well plated vias can survive only a handful of assembly passes without cracking.    Typically, 1‐2 reflow cycles are required for SMT attach, and an additional 2 reflows for each rework (remove & replace). Therefore, 8 reflow cycles of greater than 220C could be possible during assembly. A methodology for increasing the reliability of these circuit boards was to epoxy fill the vias to add strength and extend the product life.

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A DfR customer experienced cracking and separation of epoxy‐filled vias and was interested in identifying the root‐ cause that initiated cracking/separation and determining the risk to existing product in the field.  Figure 2 illustrates the issue.

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Design and Fabrication

The vias were filled as part of a process to ensure good bonding between two printed boards and an aluminum heat spreader. A 10 layer, 70 mil thick printed board fabricated with Park Electrochemical N4000‐6 (Tg 170, CTE 68ppm) was laminated and vias were drilled. The vias were 13 mils in diameter with 1.2 mil thick plating. To ensure sufficient copper thickness, a dot plate process was performed, followed by sanding process to ensure planarity.   

FEA Analyses

DfR’s customer requested that DfR Solutions use computer simulations to determine:

  • The influence of thermal transients on the thermomechanical failure behavior of the capped vias.    This is done to determine if the failures that occur during IST are a result of thermal gradients.  
  • To identify the key drivers for cracking / separation in filled vias  
  • To ensure sufficient reliability, a lifetime of 10K hours, in those units currently in operation

Assessment of stress state within the filled vias consisted of three models:

  • A full 3‐D model was constructed to assess the influence of transients. This model took into account the via and surrounding material.
  • A 2D axisymmetric model was created to assess the potential for separation/cracking in the via. At the interface of the wrap and the cap, the nodes were tied and the breaking stress required for cap separation was determined.  
  • A 2D axisymmetric model was created to assess the potential for long‐term reliability. The units out in the field were assumed to have a strong interface and therefore the strength of the interface was assumed to be similar to bulk copper. Field conditions were obtained from the customer and applied to the design to ensure 10,000 hour life

Finite Element Analysis

Abaqus™ Version 6.6‐1 and Abaqus CAE™ were used for modeling and analysis of the capped via structure.  The first simulation conducted was a transient 3D thermal analysis to determine what type of thermal gradient existed during IST.  If the gradients are significant then the IST results may cause loading conditions that can not be related to the field conditions.  The additional models are axisymmetric and are used to model separation of the via end cap from the barrel and to make life predictions to determine if the structure will survive the intended field environment.   


The structure is composed of three materials, resin, laminate and copper.  The copper has elastic plastic behavior and is modeled using a Ramberg‐Osgood equation fit to the Tyco copper test data, as shown in Figure 3.  The materials and their associated elastic and expansion properties are shown in Table 1.  Some assumptions were made for the behavior of the materials above their glass transition temperature.  The assumptions are based upon the behavior of other PCB material systems which typically show an order of magnitude drop in elastic modulus above their Tg, as shown in Figure 4.    The thermal and electrical properties used for the coupled transient thermal and electrical analyses are shown in Table 2.

dis fig2-table 2

Transient Thermal Analysis, Three Dimensional Modeling

Three dimensional FEA modeling is done to determine the thermal gradients developed during IST.  The layer structure and dimensions are taken directly from the gerber plots of the IST coupon (as shown in Figure 5).  Only a 4 x 6 grid of the plated through holes are modeled due to the complexity and number of elements required, as shown in Figure 6 (left).  A combination of brick and tetrahedron elements are utilized due to the complex structure, as shown in Figure 6 (right)

dis fig 5-6

During IST current is applied to the traces and causes the board to heat due to the resistance of the copper.   By knowing the temperature resistance relationship, the temperature of the copper can be determined and controlled.   The FEA model has current applied to the heating traces, as shown in Figure 7.    The amount of current applied during IST is not known but was adjusted so that the steady state temperature of the model was 220°C.   

dis fig 7

Axisymmetric Crack Propagation Analysis

Two dimensional axisymmetric modeling is done to determine the stresses necessary to cause the failures being experienced.  The structure of the capped via lends itself to this type of modeling due to its circular configuration.   A worst case assumption of no‐wrap is assumed for the models.    The geometric model is shown in Figure 8, and includes the via and the surrounding material.  A coupling constraint is applied to the outer circumference to force the planarity of the outer edge nodes, as indicated in Figure 9.  The mesh details in the region of interest are shown in Figure 10 and include tied contact surfaces that can debond at a set stress level, as shown in Figure 11.   

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dis fig 11

Results Coupled Transient Thermal Electrical Analysis of IST Coupon Testing

The result of the electrical thermal analysis is shown in Figure 12.  The thermal gradients are at a maximum during the ramp up to temperature and diminish as the coupon reaches steady state.  However, as shown by the figure the temperature difference within the via is very small and there is less than 0.5°C thermal gradient.    Therefore the amount of additional stress due to the thermal gradients is negligible and uniform heating of the via can be assumed.

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Axisymmetric Model Results

Two analyses are conducted using the axisymmetric model.  The first is to determine the stresses during reflow and the second is to determine if failure will occur during exposure to the expected field environment.    The life requirement is 10,000 hours, and assuming one cycle per flight event and one event per day yields a life requirement of 417 thermal cycles.  The worst case thermal cycle is assumed to be from ‐40°C to 70°C.

Crack Propagation Simulation

The first thermal mechanical analysis is done to quantify the stresses that occur during reflow and to determine if cracking of the cap structure is possible.  The temperature is ramped up from 25°C to 210°C and back down to 25°C to simulate a reflow event.  The stress required to initiate cracking is determined by adjusting the fracture criterion of the tied contact surfaces such that a partial fracture occurs after one reflow event.  As shown in Figure 3 (the stress strain plot for the copper), fracture typically occurs between 300 and 350 MPa.    

During a reflow event the stresses that develop near the via cap are very high and plastic deformation occurs.  The stresses present just prior to fracture are shown in Figure 13 and are almost 300 MPa.  During fracture the stresses are in excess of 300 MPa and cracking may occur during reflow if the interface is brittle (See Figure 14).  The plastic strains developed in the via are shown in Figure 15 and are around 8.6%.    A comparison between the FEA deformations and the cross‐section provided by Tyco is shown in Figure 16.

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Thermal Mechanical Fatigue Simulation

The model is modified to remove interfacial cracking and the fatigue predictions are made based upon the stresses and strains developed during a thermal cycle.  The thermal cycle is assumed to be from ‐55°C to 70°C and occurs a total of 417 times.  The maximum principal stresses developed in the via are shown in Figure 17, the plastic strains at ‐55°C and 70°C are shown in Figure 18 and Figure 19.  The area with the highest stresses and strains is at the inside corner where the cap connects to the barrel.

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The formula shown in Figure 20 is used to make fatigue predictions using the output of the FEA model.  The formula is taken from IPC‐TR‐579 and has been used extensively in the electronics industry.  A summary of the stresses and strains with the life predictions is shown in Table 3. 

dis fig 20 table 3


The results show that an uncracked capped via will survive over 8000 thermal cycles from ‐55°C to 70°C and will meet the assumed life requirements (10,000 hours, 417 cycles).  However, when cracking occurs this result is no longer valid and the via may fail much earlier.  As shown by the FEA results, the stresses developed in the via are sufficient to cause the initiation of a crack if the copper to copper interface is weak.   Once this crack has occurred, it will propagate along the interface and cause separation of the cap from the barrel.    This was simulated with the FEA model by adding an additional ramp up to 70°C after the 210°C temperature excursion.  Figure 21 shows the crack opening at 210°C followed by the closed but still separated crack at 25°C.  The large image in Figure 21 shows the crack propagation after an additional temperature ramp to 70°C.    This caused the crack to propagate about 20% further, and indicates that this type of failure should occur quickly and should be captured during the ESS testing (assuming thermal cycling is performed) or early in the life of the product.  

The presence of a wrap will not stop the crack initiation but will change the crack propagation path so that failure is unlikely, as shown in Figure 22.    As the crack grows, the opening stress will decrease until it is insufficient to propagate the crack.  

DfR recommended that our customer should review their ESS procedure to ensure that a sufficient number of thermal cycles are performed to capture the defects.  

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