Since 2006 RoHS requirements have required lead free solders to take the place of tin-lead solders in electronics. The problem is that in some environments the lead free solders are less reliable than the older tin-lead solders. One of the ways to solve this problem is to corner stake, edge bond or underfill the components. When considering what mitigation technique and material to use, the operating conditions must be characterized. The temperature range is important when selecting a material to use since the glass transition temperature (Tg) and coefficient of thermal expansion (CTE) are important properties. If improperly chosen, the mitigation material can cause more failures than an unmitigated component.
This study focused on 208 I/O BGAs on a 4 layer FR4 board. There were three solders tested; two lead free (SAC305 and SN100C) and one leaded (SnPb). Three mitigation techniques were tested: corner staking, edge bonding, and underfilling. Each of these techniques had two mitigation materials tested. One material was reworkable and the other was not. The boards were subjected to mechanical shock testing and sinusoidal vibration testing until failure.
The results of the testing show that no one mitigation technique is best for all of the conditions tested. The same is true for the mitigation material. The best choice of mitigation technique and material is application dependent.
With the enforcement of RoHS requirements, there has been some concern about the reliability of leadfree solders. The reliability of tin lead solder is well known as a robust solder and the failure rate is well characterized, whereas SAC solders are known to be less robust which is a problem for some high reliability applications. One solution is to mitigate the solder joints with a staking material to strengthen the joint, but the problem is choosing the correct material for the application. Several material properties, such as glass transition temperature (Tg) and coefficient of thermal expansion (CTE), need to be properly chosen. Improperly chosen mitigation materials will cause premature failures instead of extending the time to failure. If the expected operating temperature of the device is too close to the Tg, the CTE will drastically change which can cause solder joint failures as shown in Figure 1.
This study chose to focus on one component type: the Ball Grid Array (BGA). The BGAs that were chosen were 15mm by 15mm packages with 208 balls. The balls were 0.5mm in diameter and had a pitch of 0.8mm. The balls were attached to the BGA along the perimeter 4 rows deep. The BGAs were purchased with tin lead (SnPb) balls and reballed to attach the SAC305 and SN100C solder balls. The reballing process does not have an effect on the reliability of the component, it could increase the strength of the solder ball interconnect by at most 10%.  These BGAs were attached to 4 layer FR4 printed circuit boards (PCBs) as seen in Figure 2.
The PCBs arranged the components into 4 rows and 5 columns. The placement of the component was determined by first vibration mode as calculated through finite element analysis and shown in Figure 3. The figure shows that the center column and the column on either side are in the highest strain area. The two outside columns are in a lower strain area. This was done so that multiple strain levels could be investigated on one test PCB.
Three mitigation techniques were chosen for testing: corner staking, edge bonding, and underfill. These techniques were only applied to the SAC305 BGA. The materials for mitigation were chosen for their range of glass transition temperatures (Tg) and coefficient of thermal expansion (CTE). The materials were also chosen to a reworkable material and a non-reworkable material.
All of the environmental tests were performed using the ANATech 256 STD series event detector to monitor in situ the printed circuit board assemblies (PCBA) for failures. The ANATech allowed for multiple PCBA to be continuously monitored for increases in resistance. Changes in resistance indicated the presence of a crack along controlled impedance traces within the PCB, the components and the solder joints. The boards were dropped according to JESD22-B111 which states a failure criterion of a 10% increase in resistance. The ANATech was selected for resistance monitoring as it had a variable threshold resistance (set to the JEDEC standard) and the capability of sampling the boards every 200nS. The environmental testing was broken into two segments: mechanical shock testing and vibration testing. These tests were chosen due to the commonplace of these two events in environments for electronics. 
The results of the testing showed that the temperature during testing impacted the drops or cycles to failure regardless of the solder or mitigation used. The effective Tg of the board and any mitigation used causes the difference in cycles to failure.
There is no one right answer to what mitigation is best for each component type. The type of mitigation depends on the conditions the component will see in use. For mechanical shock testing at 125C, all of the mitigation techniques equally improved the time to first failure. At 25C, underfilling with material B is the best option since there were no failures during test. At -55C, underfilling with material B is the best option. At 125C under sinusoidal vibration, the best mitigation technique is edge bonding with material C or material A or underfilling with material D. If the same BGA sees -55C while operating under sinusoidal vibration, the best mitigation becomes underfilling with material D. For room temperature, the best mitigation technique for the BGA is underfilling with material B or material D or edge bonding with material A. Details will be provided in the slide presentation.
 Meschter, S. J., et al. "BGA Reballing from Pb-Free to Sn-Pb Metallurgy. “International Conference on Solder and Reliability Proceedings. BAE Systems. Johnson City, NY. 2010.
 Keener, M. “Extreme Drop Testing.” DfR Newsletter. (April 2013).
Application-driven choices reduce PCB reliability risks - Ball grid array (BGA) and quad flat pack no-lead (QFN) are the preferred packaging choices for most integrated circuit devices, but they present a greater potential for lead-free solder joint failure through thermal cycling, vibration and mechanical shock. Can the risk be properly mitigated?