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There is an ongoing debate regarding the influence of non-functional pads (NFPs) on printed board (PB) reliability, especially as related to barrel fatigue on plated through vias with high aspect ratios. To gather common practices and reliability data, industry experts were surveyed. The overwhelming response indicated that most suppliers do remove unused / non-functional pads. No adverse reliability information was noted with respect to the removal of unused pads; conversely, leaving them can lead to an issue called telegraphing. In all responses, remove or keep NFPs, the primary reason given was to improve the respective fabricators’ processes and yields. Companies that remove the unused pads do so primarily to extend drill bit life and produce better vias in the boards, which they considered the primary reliability issue. For those that keep the unused pads, the primary reason given is that they believe it helps manage Z-axis expansion of the board due to Coefficient of Thermal Expansion (CTE) stresses. However, with the newer materials being utilized for Pb-free assembly, the Z-axis CTE concern seems to have abated. In general, the companies responding did not feel that removing the unused pads would create a reliability issue. All suppliers said that their response was the same regardless of whether polyimide glass or epoxy glass materials were involved.
Non-functional pads are pads on internal or external layers that are not connected to any active conductive patterns on the layer. Figure 1 shows removal of NFPs on a single plated via.
DfR Solutions performed an industry survey of board manufacturers to learn the following:
The survey consisted of the following:
For the board described below, please answer the following questions:
What is your procedure with respect to non-functional inner layer pads?
Your name: ______________________
Company: _______________________
Email address: _____________________
The survey was sent out to 22 printed board fabrication companies.
Fourteen US printed board fabricators participated in the survey. An additional eight fabricators received the survey but did not respond.
DfR received responses from fourteen US-based PB shops. The following paragraphs provide insight into their responses for each question in the survey.
What is your procedure with respect to non-functional inner layer pads?
To summarize the surveyed PB fabricators responses:
“I'll just answer your question for the fabricator. We generally prefer to remove them unless directed otherwise to reduce automated optical inspection (AOI) time. An exception (unless directed to keep them), would be if we need the additional copper for stability in lamination (if it's a very sparse circuit layer).”
Thus it is a standard practice for this supplier to remove them.
Do you keep them or remove them as a function of board material type, overall thickness, layer count, copper thickness?
In all responses, the board material type, thickness, layer count, and copper thickness did not alter the company’s decision to either keep or remove the unused pads.
Is this a standard practice?
Regardless of whether the pads were kept or removed, every company responded that it was their standard practice.
If you remove or don’t remove non-functional pads, what is the reason for doing so?
This question provided the most interesting responses as it provided insight into each company’s reasoning.
In all cases, remove or leave, the primary reason was to improve the respective fabricators process and yields. The companies that remove the unused pads do so primarily because they want to extend drill bit life and produce better vias in the boards, which they consider the primary reliability issue. For those that keep the unused pads, the primary reason is that they believe it acts as a multi-flanged rivet to combat interlayer damage within the PB. Such delamination is the result of non-homogeneous Z-axis expansion of the board due to differences in the Coefficient of Thermal Expansion (CTE) of the disparate materials.
In general, the companies responding did not feel that removing the unused pads would create a reliability issue.
DfR did not expect to get many responses to these questions due to the proprietary nature of the data. However, some of the responses detailed how the fabricators gather appropriate data to make their decisions.
If you remove non-functional pads, do you have reliability data that you could share indicating whether there is or is not a reliability issue?
“We added two test coupons under the rails of the working panel. (See Figure 2.)The test coupon includes the min. hole size and max. hole size and our min. trace. The hole we designed included each layer's pad. When we complete the 1st copper plating, our lab cross sections these two coupons and checks the hole wall roughness, copper thickness, and the layer to layer registration. If the coupon showed any layer without an annular ring then we increase the check quantity. If the result was unacceptable then we may check all working panels and scrap the defect boards in the PTH process. Engineering would then investigate to check if the issue happened in inner layer process, lamination process or drill process. After finding the root cause, we correct the issue and replace the defective boards.”
“This is a combination of many factors. We have seen in the past when we have a high rate of gouging (.0007), we have multiple initiation points for plating folds that are always the first to fail. Having non-functional pads reduces this potential. Also depending on construction and how resin rich the stackup may be we see a higher amount of lifted pads and or actual cracking of the ED foil in the high layer count thick products that have minimal interconnects. Even though your scenario speaks about (not Pb-free) we see there are many CM’s that will still subject the product into those temperature ranges especially for selective connectors that require a solder fountain application. We did have a product for an ATE customer that had active components (slightly over your thickness as it was .188). They had multiple failures until the non-functional pads were added back and then there were no further issues. Same design just pads vs no pads. We have also seen more instances of larger layer count product coming in with the pads removed. From an electrical standpoint, the additional capacitance is not good for signal integrity so they are required to be removed. For this type of product, we need to make sure we increase the plated copper to .0015 minimum as we had seen failure with .0008 min copper thickness. We also did a reliability test with the attached pad stacks. I am not able to share the results with you due to NDA.”
Is the answer the same for epoxy glass and polyimide board materials?
All suppliers said that their response was the same regardless of whether polyimide glass or epoxy glass materials were involved.
Is the answer the same if the circuit is high speed?
Several suppliers also responded that if the board was a rigid flex configuration, then they would leave the unused pads in place to provide additional reinforcement for the Kapton Mylar flex material.
Technical papers and discussions that address this issue were also examined. (No company or individual who participated in the survey is cited in this section.) Impact to both design function and reliability are seen with the use of NFPs.
In “Signal Integrity Analysis of a 26 Layers Board with Emphasis on the Effect of Non-Functional Pads” [1], Ciccomancini Scogna shows that non-functional pads consistently impact insertion loss. Insertion loss provides information about both the quality of the signal and its bandwidth and is one major characteristic which help describe high speed interconnect behavior. Degradation of signal performance is seen when NFPs are used and improvements are achieved by removing them.
The National Physical Laboratory presented a webinar on “Through Hole Reliability for High Aspect Via Holes” [2]. Microsections of failed vias showed a high percentage of the failures were adjacent to non-functional pads, even though they were away from the center portion of the vias where failures typically occur. Failures also occurred earlier. See Figure 3 where inclusion of NFPs is shown in the leftmost, black line.
The paper, “Discussion on non functional pad removal / backdrilling and PCB reliability” [3] indicates that “the continuing trend (which as always is product design specific) is as follows: With smaller vias/higher aspect ratio (.008" / 0.2mm to .020" 0.5mm) the inclusion of internal lands is negative (10-30% reduction in long term performance). Conversely, with larger holes/lower aspect ratio (via size - .020"+ / 0.5mm+) the inclusion of internal lands is positive (10-15% increase in long term performance).”
In “Design and Construction Affects [sic] on PWB Reliability,” Paul Reid states: “Generally speaking the presence of non-functional pads is a determent to the reliability of PWBs” [4]. He further points out that one or two non-functional pads that are not in the center of the PTH generally improve reliability when compared to the same PTH with NFPs at every layer. He describes a condition call "telegraphing" where there is so much copper at PTHs the material is "resin starved" between pads and you can see the image of this "pancake stack "of copper in the dielectric; the image is "telegraphed" to the surface. When the dielectric is thin and the copper thick, the condition is exacerbated and reliability is significantly reduced. The high spots create regions where the epoxy is squeezed out. Lack of sufficient epoxy can result in adhesion issues and can provide potential pathways for electrochemical migration to occur. Reid’s schematic is shown in Figure 4. He indicated that is a condition of concern but acknowledged not seeing any real rejections for this condition.
In his book High-speed Circuit Board Integrity [5], Thierauf states that in many situations, NFPs are harmless. However, they can be troublesome in high speed signaling applications, especially with thick, multilayer boards. Figure 5 shows how a NFP can capacitively couple to a return plane, lowering the impedance seen by a signal passing along the via.
In Chapter 20 “Thermal Stress Issues in Plated-Through-Hole Reliability,” from Thermal Stress and Strain in Microelectronic Packaging [6], the authors refer to industry reports that NFPs are beneficial for PTH life. Modeling with and without NFPs of the Von Mises barrel stress was performed for epoxy glass and Kevlar polyimide multilayer boards, as seen in Figure 6.
On April 4, 2014, the Circuitnet Ask the Experts column addressed the topic: “Removal of Nonfunctional Pads from Inner Layers” where a reader asked: “Should we remove non-functional pads from inner layers. In some cases, it may be necessary to free up space between rows of pads to route additional trace data. I've read articles that favor both options. What is your opinion?” Responses from the experts included:
From these comments, it is clear that there is not a “one size fits all” approach to non-functional pad removal. Companies need to devise a strategy based on the design and materials used and document those needs clearly to their printed board fabricators. The experts do all recommend removal of NFPs where possible.
PB Fabricators routinely recommend removal of non-functional pads. Multek states that including NFPs adds unnecessary spacing and decreases layer yield [7], illustrated in Figure 7.
For improved signal integrity at higher frequencies, Sanmina indicates that removal of nonfunctional pads and via backdrilling are two commonly used via optimization techniques [8].
Altera offers guidance in at least two application notes [9, 10]. In order to minimize parasitic capacitance in high speed (Gbps) transceiver designs and to optimize vias in high speed channels in general, eliminating all non-functional pads is recommended. Altera further recommends removing NFPs in all high aspect ratio vias.
In “Practical Guidelines for Implementing 5 Gbps in Copper Today, and the Roadmap to 10 Gbps” [11], the authors recommend removal of NFPs, as seen in Figure 8.
The survey results do not indicate any specific reliability issue associated with the removal of unused pads for standard rigid multilayer boards. Two thirds of the fabricators that responded removed the pads routinely or after approval from their customer. DfR recommends that designers include this type of acceptance requirement on either their fabrication drawings or their purchase orders.
One supplier for military PBs did indicate that they felt the removal of pads could present a reliability issue. When queried further, it was determined that the issue was with very small drill bits on a 22+ layer board. In that instance, the additional stiffness from the pads provided support in the drilling operation where the aspect ratio was high.
However, some of the responses and the literature search indicate that the non-removal of unused pads could result in a phenomenon called “telegraphing” where the epoxy is squeezed so thin that there is a little left between each layer which can be a reliability issue [4].
This work was supported by those printed board fabricators who participated in the survey.
[1] A. Ciccomancini Scogna, “Signal Integrity Analysis of a 26 Layers Board with Emphasis on the Effect of Non-Functional Pads,” IEEE EMC 2008 Symposium.
[2] Wickham Martin, “Through Hole Reliability for High Aspect Via Holes,” NPL Webinar June 11, 2013.
[3] Birch, Bill, “Discussion on Non-functional Pad Removal/Backdrilling and PCB Reliability,” PWB Interconnect Solutions Inc. 103-235 Stafford Road West, Nepean, Ontario, Canada K2H 9C1.
[4] Reid, Paul, “Design and Construction Affects on PWB Reliability,” PWB Interconnect Solutions, IPC APEX EXPO.
[5] Thierauf, Stephen, High-speed Circuit Board Integrity, Artech House, January 2004.
[6] Barker, Donald & Dasgupta, Abhijit, Chapter 20 “Thermal Stress Issues in Plated-Through-Hole Reliability” in Thermal Stress and Strain in Microelectronic Packaging, Van Nostrand Reinhold, 1993.
[7] Frank, Bill, “Design for Manufacture,” Multek.
[8] Sanmina, “PCB Fabrication: Opti-Via Technology for Improved Signal Integrity at Higher Frequencies.”
[9] Altera AN-672, “Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission,” 02/15/2013.
[10] Altera AN-529, “Via Optimization Techniques for High Speed Channel Design,” May 2008.
[11] Rothermal, Brent et al, “Practical Guidelines for Implementing 5 Gbps in Copper Today, and the Roadmap to 10 Gbps,” DESIGNCON 2000. IMAGE REFERENCE
[12] Non Functional Pad Removal. http://wiki.fed.de/images/7/70/Empfehlung_zu_Non_Functional_Pad_Removal.pdf.
