Eutectic AuSn solder is increasingly used in high reliability and/or high temperature applications where conventional SnPb and Pb-free solders exhibit insufficient strength, creep resistance, and other issues. These applications include hybrid microelectronics (particularly flip chips), MEMS, optical switches, LEDs, laser diodes, RF devices, and hermetic packaging for commercial, industrial, military, and telecommunications applications. For most of these applications, AuSn provides the additional benefit of not requiring flux during reflow, significantly reducing the potential for contamination and pad corrosion. However, the materials and processing considerations are substantially different than for conventional solders. Many companies struggle with issues such as poor solder flow, excessive void formation, variable reflow temperature (arising from off-eutectic compositions), heterogeneous phase distribution, and others, all contributing to development delays, process yield loss, and field reliability issues. This paper reviews the critical issues in material and process selection, as well as long term diffusion and mechanical stability.
Key Words: AuSn, eutectic, metallization, reflow, diffusion, reliability
Eutectic AuSn is widely used in high temperature and high reliability applications due to excellent mechanical and thermal properties (particularly strength and creep resistance) and its ability to be reflowed without flux. Other Pb-free and traditional Pb-based eutectic solders suffer by comparison due to a variety of problems:
While components with AuSn solder joints have demonstrated reliable performance in demanding environments for over 30 years, the performance is based on reflow processes that produce repeatable, void- and defect-free joints. This paper was motivated by numerous requests from start-ups and established companies for advice on solder joint design, acceptable material combinations, and reflow process development.
Many of the key issues associated with AuSn soldering can be ascertained from the binary phase diagram, shown in Figure 1. The most notable features are steep liquidus lines, particularly on the Au-rich side of the eutectic composition (71 at% Au/29 at% Sn, or 80Au-20Sn by weight), and the numerous intermetallic “line” compounds at ambient temperature.
When using eutectic solder (preforms, pastes, or platings) and metallizations terminated with Au layers, the resulting solder joint will have a melting point much higher than 280ºC due to diffusion/leaching of the Au metallization into the solder. This can be advantageous for two reasons: secondary reflow of other components can be performed at the same temperature without disturbing the initial solder joint, and the higher remelt temperature generally implies greater creep resistance. However, the component may be difficult or impossible to rework; even if the two bonded adherends can be separated (by shearing or “hot-lifting”), irregular/uneven intermetallics will be left on both surfaces that prevent subsequent reflow. Additionally, solidification (“freezing”) may occur during reflow, leading to poor wetting and associated insufficient bond coverage & strength.
These disadvantages can be addressed by biasing the composition of the solder to the Sn-rich side, so that the eutectic composition is obtained after complete dissolution of the Au metallization. For preforms and pastes, this approach may be problematic due to variability in solder composition, which is one of the reasons why many applications employ AuSn deposited by evaporation, sputtering, or electroplating.
At the eutectic composition, the following compounds should be observed upon cooling: L → x + d → x’ + d. Generally, the microstructure is a fine mixture of x’ and d in the bulk of the joint, with predominantly x’ layers at the metallization interfaces. [Typical microstructures are shown in references 4, 20, and 23.]
When Au and Sn layers (single or multiple of each) are employed, sequential formation of h, e, d, and x’ is expected at the Au-Sn interface [30,31]. Generally, this approach is known as transient liquid phase (TLP), rather than eutectic, bonding. The advantage of TLP bonding is that reflow temperatures between the melting points of Sn (232ºC) and the eutectic can be employed. However, longer process times will be required, either at reflow or during subsequent annealing; furthermore, if the reaction is not completed, microstructural (and residual stress) evolution will continue over time. These disadvantages can be reduced by using thinner, multiple layers (the total number of layers will be dictated by the flatness of the two surfaces to be bonded – the total layer thickness should be greater than 3 times the roughness ). Thinner layers minimize the diffusion distances for Au and Sn, and hence the time required to obtain the eutectic composition.
The phase diagram also provides guidance regarding mechanical properties. All of the intermetallics on the Sn-rich side of the diagram are “line” compounds, with extremely limited solubility ranges. These compounds generally exhibit high strength and creep resistance, at the expense of limited ductility (brittleness). As will be discussed in a subsequent section, however, the eutectic phases do possess moderate ductility in addition to excellent creep resistance, and are much less brittle than CuSn intermetallics (common in SnPb and Pb-free solders on Cu metallization or substrates) [35,36].
Selection of appropriate coatings for the two surfaces to be bonded is critical for reliable soldering with AuSn. The general requirements are:
The contact/adhesion layer is particularly necessary for semiconductors and ceramics, as most metals will not bond directly with these covalent materials; contact layers are not usually required for metal substrates. The barrier diffusion layer must both bond well to the contact layer and be either non-reactive to Sn (intrinsic) or thick enough to prevent complete dissolution/ intermetallic formation during reflow and subsequent aging (extrinsic). The cap layer prevents oxidation of the surface prior to reflow, and is invariably composed of pure Au for compatibility with AuSn solder.
A wide range of material combinations can be used. Typical metal stacks and thicknesses (if available) are presented in Table 1. Generally, TiW/Au or Ti/Pt/Au (contact/barrier/cap layer, respectively) is used on semiconductors and ceramics, while Ni/Au is employed for metals. The Ni can be either electrolytic (pure Ni) or electroless (2-14% P), but the latter is more common due to lower cost. Studies of different barrier layers are provided for Ni, Pt, and Pd  and deposited NiSn and AuSn intermetallics on TiW .
For barrier layers that react with Sn, the dissolution rate depends on a number of factors:
Solder joint thickness
A particular example is provided to illustrate consumption of the barrier layer, based on the work of Song et al., [19, 40] and shown on Figure 2. The two papers evaluated AuSn bumps with Ni under-barrier metallization (UBM) on Cu , as well as Cu alone . The growth of both Au-Ni-Sn and CuSn intermetallics at the solder/metal interface exhibits square-root dependence with time, typical of diffusion-controlled processes, though the rate of consumption of Ni is lower by a factor of ~2.
Non-reactive barrier metals such as W, particularly when coupled with overlayers of NiSn or AuSn intermetallics, can effectively eliminate barrier metal consumption .
For nominally similar materials, reflow, and storage conditions, the consumption rates can vary substantially. As barrier metal grain size decreases, consumption rates will be increased due to enhanced grain boundary diffusion (contributing to bulk diffusion). Residual stresses associated with various phases may not only modify diffusion rates, but also be sufficiently high to initiate yield and cracking .
For the studies covered in this paper, the types of solder include preforms, pastes, and deposited films. Film deposition techniques include sputtering, evaporation, and electroplating, involving either single or multiple layers. Brief overviews of the advantages and limitations of each are as follows, along with the associated work referred to in this paper:
Generally, electroplating of single layers with the eutectic composition or multiple layers of alternating Au5Sn (x’) and AuSn (d) is regarded as having the potential for the most manufacturable, high volume process. However, for proof-of-concept and/or low volume parts, preforms, sputtering, or evaporation may be acceptable.
Guidance on actual process conditions is the most difficult to provide, given differences in: size, weight, flatness, and CTE for components & substrates; solder joint size and gas access during reflow; reflow equipment (ovens, die bonders, IR/laser reflow, hot plates, etc.); associated thermal mass and heating/cooling rates; and more. The following statements are generally true:
Particular solder process parameters for a variety of applications and bonding equipment are summarized in Table 2.
The mechanical behavior of solders and intermetallic compounds, especially for use as inputs in finite element analysis (FEA), are typically based on measurements obtained from bulk samples (often produced by arc melting). However, the values obtained from such measurements are usually misleading, due to significant differences in grain size, residual stresses, and mechanical constraint compared to typical solder joints, joint geometries, and material combinations.
Table 3 summarizes the mechanical properties of metals, solders, and relevant intermetallic compounds obtained on actual solder joints or thin film samples. The intermetallic data shown here is entirely from the work of Chromik et al. [35,36], which employed nanoindentation – they provide a detailed discussion of the advantages and limitations of nano-indentation compared to bulk techniques (die and lap shear; resonance; micro-indentation). That same technique was also used to obtain indentation creep data, shown in Figure 3, which validates the high creep resistance of both individual AuSn & Au5Sn phases as well as the eutectic composition itself .
The effect of Sn diffusion into and subsequent consumption of barrier metal layers was discussed previously. Here, the interdiffusion of Au and Sn is reviewed to provide guidance for applications using single or multiple layers composed of Au and Sn, such as TLP bonding. Somewhat surprisingly, while Sn is the lower melting temperature element, Au is the faster diffusing species when bulk (interstitial) diffusion dominates, due to its lower atomic radii [30,31,32,39]. As the grain size of the Au layer(s) decreases, interdiffusion may be equal or the situation reversed due to faster diffusion of Sn along Au grain boundaries . Differences in interdiffusion rates drive the initiation and growth of Kirkendall voids; an example can be seen in Reference 30 (Fig. 2 of that paper).
Excellent measurements and analysis of intermetallic formation rates at varying annealing temperatures were performed by Yamada et al. [31,39]. Diffusion couples were composed of a single layer of Au between two layers of Sn. In all cases, the three intermediate Au-Sn intermetallic compounds (AuSn4, AuSn2, and AuSn) exhibited a power law relationship with annealing time, and the ratios of each layer thickness to the total intermetallic layer thickness remained constant at a given temperature. The ratio decreased with increasing temperature for AuSn4, while increasing for AuSn2 and AuSn .
The total intermetallic layer thickness, l, as a function of time, t, was described according to the following equations:
where the exponent, n, and proportionality constant, k, depend on temperature, to and ko are constants, Q is the activation energy, R is the gas constant (8.3144 J/mol-K), and T is the temperature in Kelvin.
An assessment of the intermetallic layer thicknesses at a given temperature and time is illustrated in Figure 4a. The cumulative layer thickness as a function of annealing time and temperature is illustrated in Figure 4b. Fits of Equation 1 are shown, with associated time exponents. The constants in Equation 2 were subsequently determined to be ko=1.33 and Q=55.6 kJ/mol.
The behavior of thinner deposited layers is expected to be different due to the effects of grain boundary diffusion of Sn, but these studies nonetheless provide a framework for evaluation and analysis.
Given its high strength and creep resistance, solder joints composed of eutectic AuSn are extremely stable in a broad range of harsh environments. These include thermal cycling from -55 to +125ºC [5,8,9,13], high temperature storage from 75 to 150ºC [5,9,18], high temperature/high humidity in 121ºC autoclaves , die or double lap shear after extended aging up to 250ºC [18,33], and extended operational performance for laser diodes [11,37].
The primary reliability issues arise from defects introduced during processing (voids, irregular phase formation, weak interfaces due to insufficient barrier metals, etc.) that act as crack initiation sites. While the previous section demonstrated that the two eutectic intermetallic phases possess some ductility, bulk solder joint fracture is typically brittle, and hence linear elastic fracture mechanics is the best methodology for estimating lifetime. Worst-case defect sizes should be based on the limits of non-destructive evaluations & process monitoring capability.
This paper provides a review of the critical material and processing issues associated with eutectic AuSn soldering, as well as diffusion rates for multi-layer structures and mechanical behavior. With appropriate design and process development, AuSn solder joints exhibit superior performance in a variety of demanding application environments.
The author would like to thank Kenneth Scholz and David Schleuning of Coherent, Inc., for many helpful discussions.
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We investigated Intermetallic compound formation mechanisms and their effect on the integrity of ball grid array Cu/Ni/Au/solder joints integrity were investigated. Substrates with three types of Au plating, and thus three different thicknesses [ Electrolytic (2.6 and 0.75pm). Immersion (0.25pm), and Selective (0.02pm) ] were used.
Gold embrittlement in SnPb solder is a well-known failure mechanism in electronic assembly. To avoid this issue, prior studies have indicated a maximum gold content of three weight percent. This study attempts to provide similar guidance for Pb-free (SAC305) solder. Standard surface mount devices were assembled with SnPb and SAC305 solder onto printed boards with various thicknesses of gold plating.