Recent advances in 3D package reliability

By Craig Hillman

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The hard and fast truth is that Moore’s law has been dying a slow death for years. When Moore’s Law was first released in 1965, transistor count was supposed to double every year. Moore himself modified the law 10 years later, in 1975, to every two years. However, more recent history has indicated that semiconductor performance is not keeping pace. From 2005 to 2012, transistor count has actually been doubling almost every three years (2.8 to be exact [1]), with Intel being the primary driver. And with Intel’s last two node size development cycles extended from 2 years to 2.5 years since 2012 [2], Moore’s Law is now likely running closer to a doubling every four years.

With this eventual slowing of progress on the silicon side (not to mention the astronomical capital costs) [3], an increasing focus has been on the development of new and innovative packaging to allow semiconductor technology to continue to keep pace with market expectations of performance. The leading approach has primarily been in the area of 3D packaging. But, what is 3D packaging? The term 3D packaging can be more marketing hype than a specific technology or architecture. But to discuss reliability advances, we need to clearly define 3D packaging. In a broad sense, 3D packaging can be defined as: A packaging configuration that consists of more than one plane of active elements. Within this definition, there are four subcategories of 3D packaging:

Stacked cells/transistors. In this arrangement, the 3D packaging is on a single die. Examples of this technology include 3D NAND Flash being developed by Samsung [4], Toshiba, and Intel/Micron.

Stacked die. This consists of multiple die within a single package and is already common in memory packages, but a new generation is being released that replaces wire bond connections with through-silicon vias (TSV). An extreme example of this 3D package sub-category is Micron’s Hybrid Memory Cube.

System-in-package. This sub-category goes beyond simple multi-chip modules (MCM). Instead, envision an encapsulated device with multiple technologies, including memory, integrated devices, discretes, passives, and magnetics. Some older versions of the Enpirion DC-DC converter are excellent examples of this.

Stacked package. For this configuration, two packages with either single or stacked die, are stacked one on top of the other. (Author’s note: While there are great images and prototypes of more than two packages stacked on top of each other, commercially, this author is only aware of dual package stacked configurations.)

Separating out each sub-category is critical because reliability is driven by the interaction between materials, geometry, and environment—and each of these sub-categories are different in that regard.

Reliability of stacked cells/ transistors

The latest in reliability of stacked cells is better news than often experienced with advances in semiconductor packaging. The major driver for the good news is the increase in feature size that is obtainable with stacked cells. As an example, there are strong indications that the Samsung 3DVNAND Flash (Figure 1 [5]) is fabricated at a 40nm process node [6-8], compared to the existing 16nm process node for 2D planar NAND Flash.

rec fig 1

The latest in reliability of stacked cells is better news than often experienced with advances in semiconductor packaging. The major driver for the good news is the increase in feature size that is obtainable with stacked cells. As an example, there are strong indications that the Samsung 3DVNAND Flash (Figure 1 [5]) is fabricated at a 40nm process node [6-8], compared to the existing 16nm process node for 2D planar NAND Flash.

It would be nice to make a statement about the reliability of other stacked cell technologies, but they are currently clouded in secrecy, late to market, or both. Toshiba, Hynix, and Intel/Micron are all promising 3D NAND shortly, but have provided little details to determine if, or how, their structure or materials would influence FIT rates or long-term performance. For example, there are indications that the 3D NAND device being proposed by Intel/Micron is using a completely different memory technology (such as resistive RAM).

Reliability of stacked die

If stacking of transistors is not feasible, and this is still the case for semiconductor logic circuits, the next best thing is to stack the silicon itself. The stacking of silicon die is likely the most common category of 3D packaging, with most high-capacity memory devices having two or more stacked dies.

The biggest quality/reliability issue with stacked die is primarily ensuring known good die (KGD). Test coverage can tend to be limited when doing wafer probing. A better understanding of die functionality and defects is often not captured until after packaging. This is why most stacked die packaging comprises no more than four die. The dominant interconnect structure within stacked die is wire bond and will remain wire bond for the foreseeable future as recently shown by Chet Palesko and Jan Vardaman [11]. The reliability challenge for stacked die and wire bonds has been the recent change from gold to copper wire bonds.

Except for corrosion resistance, the material properties of copper wire bonds can be surprisingly similar to gold. There is a relatively small difference in melt temperature (1085°C vs. 1064°C), so basic diffusion processes would be expected to be about the same (more on this later). Pure copper tends to have a higher yield strength than gold, but this is very dependent on purity levels, anneal temperatures [12] and strain rates [13]. (Author’s note: “Tends” is the operative word, as several references have published conflicting values when comparing gold vs. copper wire.) Copper does have a higher modulus (117GPa vs. 74GPa) and a higher coefficient of thermal expansion (17ppm/°C vs. 14ppm/°C), so stresses due to thermal cycling will be higher with copper wire bonds (as much as 2X higher).

While reliability under temperature changes may be compromised, reliability under constant temperature is actually much improved because of the particular behavior of aluminum. Aluminum, which is the bond pad material of choice, has a much higher solubility [14] and diffusion rate [15] in gold than copper. This will greatly extend the timeto-failure (and temperature of failure) for classic wire bond failure mechanisms such as purple plague and Kirkendall voiding.

The greatest risk with copper wire bonds and stacked die, in addition to corrosion/ oxidation under humidity and thermal cycling, is preventing defects and damage during manufacturing on account of the narrower process window. For the most part, this expectation has been borne out by published studies on the copper wire bond reliability (Table 1). There have been several reported issues with copper wire bond failures in automotive applications that all seem to point back to process or quality control issues [16]. Similar experiences were reported by iNEMI [17].

While the transition to copper wire bonds has been a challenge, the real performance improvement with stacked die (so critical in maintaining Moore’s Law) is expected to come with through-silicon vias (TSV). The concept of through-silicon vias has been around almost as long as the integrated circuit, with some of the original proposals patented back in the 1960s [18]. While there is some debate about their first commercial application, until recently, TSVs were limited to silicon-based hermetic packaging (Agilent/Avago’s Microcap for film bulk acoustic resonator [FBAR]) and CMOS sensors (Toshiba, Aptina, Sony). One of the challenges in predicting the reliability of TSVs is the broad range of potential processes, materials, and design available. One practical approach is to look at commercially available technologies using TSVs, such as Microcap and CMOS sensors, and assess their reliability performance.

The original Microcap packaging, patent filed in 1999 [19] and commercially released in 2004 [20], is a die-to-die bonding process used to maintain a hermetic environment around FBAR technology. The original design was not a true TSV package as the interconnect was a wire bond connection through a hole in the silicon (Figure 2a [21]). However, to ensure a lower profile, the Microcap was then revised with a true TSV architecture (Figure 2b [22]). TSVs for CMOS image sensors were first introduced by Toshiba in 2008 (Figure 3) [23]. The driver for TSVs was the ability to maximize the pixel area array for the given footprint and it allows for the pixel array and logic circuits to be fabricated with different process nodes.

Do these existing TSV structures demonstrate sufficient reliability for extended life applications? Given the application and design, the field data is likely insufficient. The dominant (think >95%) market for FBAR is cell phones. This is a relatively benign environment (at least from a thermal cycling perspective) and a very short lifetime (2 to 3 years, maximum). Stacked chip image sensors are in a similar situation. For the most part, CMOS image sensors with TSVs are only found in very high-volume manufacturing (think cell phones) [24].

Concerns about TSV reliability inexisting applications is not only driven by the expected use environment, but also by the design. As stated by Caswell [25], TSVs have three primary failure mechanisms: cracking of the plating, cracking of the silicon/change in resistance of silicon, and interfacial delamination of the via wall from silicon (which can result in TSV extrusion). In regards to the Microcap, cracking of the plating is unlikely because the silicon has a lower coefficient of thermal expansion (CTE) than the gold plating. Any increase in temperature, due to hot spots or change in ambient conditions, will place the gold plating under an axial compressive stress. (Author’s note: Cold temperatures will place the plating under axial tension and could potentially induce barrel cracking. However, the way most semiconductor manufacturers test their product, -55°C or -40°C to +85°C or 125°C, will NOT induce this failure mechanism. This is because the mean stress under these conditions will be negative, assuming a zero stress state at room temperature, which effectively results in infinite lifetime. Running a thermal cycle test between room temperature to -40°C could result in rapid failure.) The tensile stress then arises circumferentially and could induce cracking along the length of the via, but will not cause electrical failure. Cracking of the silicon is unlikely because the TSV is not filled, which reduces the stress due to differences in CTE.

rec table 1 fig 2-3

rec fig 4-6

However, interfacial delamination is very likely. In fact, a recent teardown of a Microcap by System Plus Consulting [26] clearly shows the gold separating from the silicon wall (Figure 4, see yellow arrow). The risk of this delamination likely explains the toothed structure of the gold on the cap. This arrangement effectively prevents the interfacial delamination from propagating around the cap and causing a reduction in hermeticity.

The TSV in CMOS image sensors have a very different design than the Microcap. While their TSVs are also likely laser drilled (due to the sloped sidewalls) and plated using electrochemistry (due to the relatively small aspect ratio), the CMOS image sensor TSVs observed in tear downs are fully filled. The fully-filled TSVs will effectively eliminate any risk of plating cracks, but does greatly increase the stresses within the silicon. The stresses within the silicon can be approximated using the Lame stress solution for both cylindrical and Cartesian coordinates.

While there is some debate regarding the usefulness of the Lame approximation vs. finite element analysis, both approaches reported by numerous authors have calculated extremely elevated stress levels in the silicon on account of the TSV structure. As an example, a recent paper by Moongon Jung [27] reported von Mises stress levels up to 800MPa in the silicon and in the interface when the TSV structures are spaced approximately 10µm apart (Figure 5).

Unfortunately, the authors in [27] failed to realize that von Mises stress and the risk of silicon deformation is not the relevant concern. The potential for cracking of the silicon should hopefully be minor, as the device manufacturers would be expected to develop a process that did not induce cracking on a regular basis (and metrology that could pick up any silicon cracking). A more moderate concern is fatigue of silicon. The fracture strength of silicon can be as low as 1GPa and fatigue of silicon has been reported at levels as low as 50% of the fracture strength (Figure 5) [28].

However, the greatest risk in regards to TSV is interfacial failure. The stresses, regardless of methodology being used, peak at the interface. The strength and other properties of common interfacial materials (SiO2 and benzocyclobutene [BCB]) are poorly understood, especially at the length scales relevant to TSVs. And, as with plating cracks, the true reliability of the interface is likely poorly understood by device manufacturers because of their blind reliance on standard thermal cycle testing, which will likely overestimate lifetime because of its tendency to swing stress states from tensile to compressive and back, and potentially lower the mean stress state to levels below those expected in field applications.

Up until now, the uncertainty regarding TSV reliability has not been a concern given the application environment of 99% of devices with TSVs (cell phones). However, two TSV devices with a broader range of applications recently were introduced into the market. Xilinx introduced its Virtex 7 2000T back in 2012, where TSV architecture is used on a silicon interposer (Figure 6a [29]). More recently, in November 2015 [30], Samsung introduced a new type of DDR4 DRAM DIMM memory for servers labeled 3DS TSV (Figure 6b [31]). (Author’s note: This is also an excellent example of the key challenge for 3D packaging, i.e., price. This new part has 2X the capacity of a similar part, but is 4X the cost.) Unlike the Xilinx part, the TSVs in Samsung’s part are integrated into the active silicon.

Not only are the intended use environments different from cell phones (likely enterprise/ server), but the fabrication processes are also likely different. The vertical sidewalls suggest an etch process, instead of the laser drill likely with the Microcap and image sensors. Plating the higher aspect ratio (approximately 5 to 6X) also may require chemical vapor deposition (CVD), instead of the electrochemical processes currently being used. Use of CVD will greatly increase stress states as that process is typically performed at temperatures between 200°C and 400°C (compared to room temperature for electrochemical). However, on the plus side, any temperature cycling will be under a single stress state (and therefore more relevant to extrapolate to field conditions).

Reliability of system-in-package

The reliability of a system-in-package (SiP) platform can be very hard to capture (even harder than for TSVs). This is primarily due to the even wider range of potential materials and designs within a SiP. A representative example [32] – an Enpirion DC-DC converter – is shown in Figure 7. This SiP has wire bonds and semiconductors, but also has ferrite, capacitors, and copper windings.

Because an SiP can effectively be a module or assembly that is miniaturized and encapsulated, all of the standard concerns regarding PCBAs can apply to SiPs. However, one unique aspect of SiPs, and one that is getting harder all the time, is the effect of the encapsulant material.

Traditional encapsulant material used in semiconductor packaging, and by default in SiP packaging, is typically filled epoxy. The fillers are fused silica spheres with typically a bimodal or even trimodal distribution to ensure up to 90% filler content by weight (approximately 82% by volume). (Author’s note: The theory of random close packing (RCP) states that the maximum volume percentage of spheres with similar size is 63.4% [33, 34]. However, a bimodal distribution can theoretically reach 93% by volume if the second distribution is approximately 10X smaller than the first.) This very high level of filler (current molding compounds are pretty much fused silica with an interconnecting network of epoxy) is driven by market demands for low coefficient of thermal expansion (fused silica has a CTE of ~1ppm/°C) and low levels of moisture sensitivity (MSL 3 or less).

rec fig 7

The very high level of filler cited above can cause other issues, especially in regards to rheology of the mold flow and elevated levels of mechanical stresses as the molding compound shrinks and hardens during the curing process. To help compensate, an increasing number of molding compounds manufacturers have started to inject epoxy formulations with lower glass transition temperatures (Tg). These formulations not only provide some protection from mechanical damage, they can also help balance the other 20+ performance requirements [35]. As seen in Table 2, Mold Compound D, with the lowest Tg, has one of the lower flex moduli and hot hardnesses, but also has the lowest conductivity and chlorine levels.

The problem with low Tg molding compounds is the change in material properties as the use or test temperature comes close to or passes through the Tg. The Tg is a critical inflection point because it is an amalgamation of changes to the polymeric structure driven by differences between intramolecular bonding and intermolecular attraction [36]. As the epoxy approaches the Tg, the increase in atomic vibration starts to overcome the secondary bonding forces (i.e., van der Waals) that constrain the polymer chain segments. This results in an increase in the free volume, which drives an increase in CTE. Once the vibration levels reach a critical level, the chains have sufficient energy to undergo significant rotational and translational motion. This results in a significant decrease in modulus. Because lower levels of energy are required to increase free volume compared to increases in movement along the polymer chains, the CTE changes before the modulus (Figure 8).

This change in CTE before the change in modulus can result in circumstances where the molding compound greatly expands without any reduction in stiffness, resulting in a significant rise in stress on the internal components that make up the SiP architecture. A simple compatibility of displacements exercise shows that stresses at or close to the Tg can be up to 5X larger than at temperatures on either side of the Tg (Figure 9).

This change in material properties can also result in a change in the mode of the stress state. Most reliability models and test plans assume primarily a shear, or Mode II, stress direction. However, these changes in material properties can drive an increase in the tensile, or Mode I, stress direction, which can greatly increase the risk of cracking or fracture of the components or interconnections (wire bond, solder) (Figure 10).

rec table 2 fig 8-10

The real challenge in regards to SiP reliability is correlating test conditions to actual field usage. Because there is a rapid change in stress and direction, test conditions, just like with TSVs, can induce a mean compressive stress that would extend lifetime almost indefinitely, while field use could have a mean tensile stress that would cause failures rapidly. Selection of the mold compound for SiP packages therefore becomes a critical step in ensuring reliability of 3D packaging.


The revolution of 3D packaging is exciting and critical for maintaining pace with Moore’s Law (even though it has slowed quite substantially). However, success with this new approach to component performance requires meticulous understanding of the thermal and mechanical risks of this new architecture. Both component manufacturers, outsourced semiconductor and test suppliers (OSATs) and OEMs must develop knowledge as to the potential risks of a “test-first” mentality and overreliance on qualification activities. Through the judicious use of physics of failure, designers, manufacturers, and users can develop high confidence in 3D packaging of all stripes, and the technology revolution built upon device performance can continue on into the indefinite future.


Craig Hillman received a BS in Metallurgical Engineering and Material Science and Engineering and Public Policy from Carnegie Mellon, a PhD in Material Science from the U. of California Santa Barbara, and was awarded a postdoctoral fellowship at Cambridge U. in England. He is CEO and Managing Partner of DfR Solutions; email


  1. J. Chen, “Analysis of Moore’s Law on Intel processors,” Proc. of the 2013 Inter. Conf. on Elec. and Information Tech. for Rail Transportation, Vol. II, pp. 391-400.
  2. D. Reisinger, “Keeping up with Moore's Law proves difficult for Intel,” CNET, keeping-up-with-moores-law-provesdifficult-for-intel/
  3. G. Yeric, “Moore’s Law at 50: Are we planning for retirement?” IEDM (12/7- 12/9 2015), Washington, D.C.
  4. S. Chen, “Review: Samsung 850 Pro 512GB SATA SSD, Custom PC Review, June 2014, http://www. samsung-850-pro-512gb-sata-ssdreview/21430/3/
  6. A. Walker, “Samsung’s 3D V-NAND Flash product – the spires of El Dorado?” 3DInCites, Aug. 12, 2014.
  7. J. Hruska, “New manufacturing technology enables vertical 3D NAND transistors, higher capacity SSDs,” ExtremeTech, June 27, 2012; http://www.extremetech. com/computing/131777-newmanufacturing-technology-enablesvertical-3d-transistors-highercapacity-ssds
  8. J. Hruska, “Toshiba readies its own 3D NAND to take on Samsung, Micron,” ExtremeTech, Mar. 26, 2015; http://www.extremetech. com/extreme/202027-toshibareadies-its-own-3d-nand-to-takeon-samsung-micron
  9. J. Hruska, “Planar NAND flash is dead: All hail our new 3D NAND overlords,” ExtremeTech, Aug. 6, 2015; computing/211812-planar-nandflash-is-dead-all-hail-our-new-3dnand-overlords
  10. A. Hava, et al. "Integrated circuit reliability prediction based on physicsof-failure models in conjunction with field study,” Rel. and Maint. Symp. (RAMS), Proc., Annual, IEEE, 2013.
  11. C. A. Palesko, E.J. Vardaman, "Cost comparison for flip-chip, gold wire bond, and copper wire bond packaging," Elec. Comp. and Tech. Conf. (ECTC), 2010 Proc. 60th, pp.10- 13, June 1-4, 2010.
  12. K.S. Kim, et al., "Relationship between mechanical properties and microstructure of ultra-fine gold bonding wires,” Mechanics of Materials 38.1 (2006): 119-127.
  13. S. Abdullah, et al., "Effects of strain rates on the characterization of 99.99% gold wire: a case study in micro tensile test,” Proc. of the 1st WSEAS Inter. Conf. on Materials Science, World Scientific and Engineering Academy and Society (WSEAS), 2008.
  14. S. Murali, N. Srikanth, C. J. Vath, "An analysis of intermetallics formation of gold and copper ball bonding on thermal aging,” Materials Research Bulletin 38.4 (2003): 637-646.
  15. S. Fujikawa, K. Hirano, "Diffusion of gold and copper in aluminum,” Trans. of the Japan Institute of Metals 12.6 (1971): 434-441.
  16. J. McLeish, R. Schueller. "Ensuring suitability of Cu wire bonded ICs for automotive applications,” Inter. Symp. on Microelec. Vol. 2015. No. 1; Inter. Microelectronics Assy. and Packaging Soc., 2015.
  17. H. Fu, “Cu wire bonding – Cu wire reliability project status,” presentation can be found at: https://www-bsac. publication.php?pdfID=1365520785
  18. K. P. Stuby, "Hourglass-shaped conductive connection through semiconductor structures,” U.S. Patent No. 3,648,131. 7 Mar. 1972.
  19. R.C. Ruby, et al., "Microcap waferlevel package with vias,” U.S. Patent No. 6,228,675. 8 May 2001.
  20. History of contribution – Agilent Labs: timeline of success; http://www.
  21. R.C. Ruby, et al., "High-Q FBAR filters in a wafer-level chip-scale package,” Solid-State Circuits Conf., 2002; Digest of Tech. Papers. ISSCC, 2002 IEEE Inter. Vol. 1., 2002.
  22. M. Small, et al., "Wafer-scale p a c k a g i n g f o r F B A R - b a s e d oscillators,” Frequency Control and the European Freq. and Time Forum (FCS), Joint Conf. of the IEEE Inter., IEEE, 2011.
  23. P. Garrou, IFTLE 172 Sony TSV stacked CMOS image sensors finally arrive in 2013, “Insights from the leading edge” blog, Solid State Technology, Dec. 2013.
  24. F. von Trapp, “The future of image sensors is chip stacking,” 3D InCites,
  25. G. Caswell, C. Hillman, “Predicting the reliability of zero-level TSVs,” additional conferences (Device Packaging, HiTEC, HiTEN, & CICMT): Jan. 2012, Vol. 2012, No. DPC, pp. 1-38.
  26. “Avago MEMS filter: The highest volume production MEMS using TSV, Solid State Technology, Mar. 13, 2013, page/89/
  27. M. Jung, et al., "TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC,” Communications of the ACM 57.1 (2014): 107-115.
  28. R.O. Ritchie, "Failure of silicon: crack formation and propagation,” 13th Workshop on Crystalline Solar Cell Materials and Processes; Vol. 42. 2003.
  29. S. Leibson, EDA360 Insider, 3D Thursday: “More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?,” Apr. 2011, https://eda360insider.
  30. “DocMemory, Next big thing for D D R 4 M e m o r y – 3 D S D D R 4 devices,” http://www.simmtester. com/page/news/showpubnews. asp?num=186
  31. “Samsung 3D TSV-based chip stacking – through-silicon vias finally show up in the real world,” Chipworks: July 2015, https:// technology-reports/recent-reports/ samsung-3d-tsv-based
  32. line-cards/altera-enpirion
  33. G. D.Scott, D. M. Kilgour, "The density of random close packing of spheres,” Jour. of Phys. D: Appl. Phys. 2.6 (1969): 863.
  34. J. G. Berryman, "Random close packing of hard spheres and disks,” Phys. Review A 27.2 (1983): 1053.
  35. P. Procter, “Mold compound,” Solid State Technology, Oct. 2003, mold-compound/
  36. “Polymer Science and Technology,” Ch. 4: Thermal Transitions in Polymers, R. Oboigbaotor Ebewele, CRC Press, 2000.



Package technology is constantly improving in order to keep up with the advances in silicon technology. Multi layered packages exhibit several failure modes that can be predicted using modern software tools. This paper provides a methodology for creating a high-fidelity model of the interposer with all the conductor geometries. The two failure modes that are explored with this model are package warpage prediction due to actual copper imbalance and filled microvia delamination. Each layer can meshed based on the actual geometry in the layout design. Package warpage is caused by copper imbalance between the two sides of the interposer.



The future of electronic package is 3D. From stacked die to Intel’s recent introduction of the 3D transistor1, the continued progression in Moore’s Law is being accomplished by going ‘up’. For the majority of design engineers, nowhere is this trend more concrete then the increasing utilization of components offered with a package-on-package (PoP) architecture.