This paper presents the defects that occur during the assembly and manufacturing of solder joints in single-sided insertion-mount printed wiring boards (PWBs). Each type of defect is discussed, with particular focus on how these defects are related to solderability issues, the mechanisms of failure due to defect-induced failure accelerators, and the effect of the defect on solder joint reliability.
Keywords: solder, failure accelerators, defects, reliability, singled-sided CEM printed wiring board, energy-partitioning model
A large amount of attention has been devoted to multi-layer printed wiring boards (PWBs) using surface-mounted components. However, there is still a strong and growing demand for single-sided insertion-mount boards. The primary end users tend to be the automotive, consumer, industrial, and telecommunication sectors, who require affordable, but not necessarily the most high-end technologies . The benefits of using a single-sided insertion-mount board include: short design and production time, compatibility with mature wave soldering processes, and low cost, provided that the number of components and the required interconnection density do not necessitate the use of double-sided or multilayer architecture.
Once the layout of the PWB is designated, the selection of an appropriate laminate system will be dependent upon the parameters of the operating specifications and usage environment. The glass transition temperature, mechanical strength, thermal expansion coefficient, moisture absorption, and dielectric properties can have a synergistic effect on the reliability of the PWB and its interconnects. One of the more common substrates used in low-cost electronic packaging is composite epoxy material (CEM) laminates. CEM laminates are defined by architecture and material composition, with some minimum performance specifications . NEMA grade CEM-1 laminates are composed of a cellulose paper core, sandwiched between two plies of continuous woven glass fabric, infiltrated with an epoxy resin binder. The composite structure allows for superior punchability and low cost while maintaining acceptable mechanical, thermal, and electrical properties. With proper tailoring of the epoxy resin, the CEM-1 laminate can provide reliability similar to the more commonly used FR-4 substrate while providing the cost advantages of a strictly paper-based laminate system.
With the use of low cost substrates (single-sided CEM), achieving high reliability requires a thorough assessment of the assembly process, soldering process, and the operating environment. With this understood, single-sided insertion-mount solder joints can yield acceptable durability in many Created: 5/14/99 applications. This begins with the realization that the manufacturing step is especially crucial, where quality control and continuous monitoring during the soldering process must be strictly maintained.
Wave soldering is commonly used to permanently connect insertion-mount components into singlesided PWBs. The components are first inserted into the board and an organic flux is applied over the terminals. The PWBs then advance through a preheat stage before arriving above a molten solder bath. A pump within the solder bath creates a single or double freestanding wave of solder. The PWBs are passed above the solder bath so that the component leads are immersed in the top of the standing wave. The molten solder forms a strong bond at the top of the lead without flowing down through the punch hole. The quality of the solder joint depends on a variety of factors, including the size and shape of the standing wave, temperature and velocity of the solder bath, and length and temperature of the preheat. In addition, the quality of the solder bath is susceptible to degradation over time due to buildup of contaminants. A non-optimized soldering process will promote the appearance of defects within the solder joint, which can increase the probability of solder joint failure in the field.
Failure of the solder joint in electronic products can arise either when individual overstress events exceed the strength of the solder joint; or when the accumulation of damage due to cyclic loading exceeds its fatigue strength. In-service reliability of well-designed and well-built solder joints is usually governed by the fatigue endurance. In single-sided PWBs, the solder joint fatigue endurance is very sensitive to the occurrence of defects in the solder. Failure accelerators can include voids, solder mask defects, misalignment of the terminal, low terminal height, poor intermetallic formation, and lack of wetting at the terminal and pad interfaces. The purpose of this paper is to describe, for single-sided insertion-mount PWBs, the characteristics of a good joint, the defects commonly observed, the source of these defects, and their effect on reliability.
An example of a good solder joint in a single-side insertion-mount CEM-1 PWB is illustrated in Figure 1b. The joint is well formed, showing symmetry on all sides, with the solder sloping from the terminal tip outwards to the board at approximately 45 degrees. Both the component-side and solder-side fillets between the terminal and the hole walls are well formed. The terminal is centered and is at an appropriate height in the hole. The solder microstructure is uniform and no voids are present. Inspection of the solder/terminal and solder/copper interfaces, using electron microscopy, shows a continuous bond with good intermetallic formation (shown in Figures 2a and 2b).
If the primary loads are cyclic in nature and below the ultimate strength of the solder joint, the failure mechanism of a strong solder joint will tend to be low-cycle bulk solder fatigue. Figures 3a through 3c show an example of single-sided solder joints that failed due to fatigue cracking. In Figure 3a, the top of the terminal displays wrinkling of the solder surface and micro-cracking, surface evidence of internal fatiguing. The crack has propagated 360 degrees around the terminal, running through the bulk solder and not at the solder/terminal or solder/pad interfaces. Figure 3b illustrates the cross section of this terminal. The fatigue crack propagation path in the solder is the trajectory of maximum shear deformation. Since this is also the eventual trajectory of the contiguous fatigue crack through the solder material, large solder microstructural domains adjacent to the crack faces will accompany cyclic fatigue, as shown in Figure 3c.
Failure accelerators are defined as defects introduced during assembly and production, which due to their composition, size, shape, or location, reduce the strength of the product (solder joint) to levels below that initially anticipated by the designer. These defects may enable overstress failures to occur, but usually lead to degradation of the product (solder joint) durability, initiating failure events early and reducing the mean-time-to-failure.
Solder masks are photoimageable polymer coatings applied to printed wiring boards (PWBs). These coatings prevent the adhesion of solder in these areas where it is not required or desired. The solder mask process involves depositing the coating, developing the desired pattern, removal in those areas designated for solder, and baking for a final cure. Solder is then applied by way of hot air solder level (HASL) to areas where the copper is still exposed.
Optimization of the formulation, application, and development of the solder mask is critical. Defects due to poor formulation, presence of contaminants, inadequate curing, or inability to produce fine features will increase the likelihood of rework, scrap during assembly, a costly reduction in product lifetime. Figure 4 shows an absence of solder on a pad around a through-hole due to an error in the solder mask pattern. This defect will be present in all units produced with this setup.
One of the most common defects observed in solder joints are voids. Small voids tend to be primarily cosmetic defects, especially when they are not located in the regions of maximum shear strain. This is because the stress concentration from a spherical defect is low and will be significantly reduced due to plastic and creep deformation in the surrounding solder. Larger voids can accelerate premature failure by significantly decreasing the net cross-sectional area, hence increasing the stress. In addition, the presence of large voids can cause local perturbations in the crack initiation site and change propagation paths due to stress re-distribution. An example of a single-sided solder joint that failed prematurely due to the presence of a large void can be seen in Figure 5.
Voids can be due to inadequate escape of gasses produced during the wave soldering process. This phenomenon, called "out-gassing", can be due to poor design, which results in inadequate pathways necessary to allow the escape of volatile by-products during soldering. Voids can also be introduced into the solder joints by excessive amounts of flux, poor selection of flux properties, presence of contaminants in the solder bath, solder drainback, and poor wetting.
Poor terminal seating can cause defects if alignment and height are not as per design. The alignment of the terminal is known as terminal registration. The Institute for Interconnecting and Packaging Electronic Circuits (IPC) document on component packaging and interconnecting, IPC-SM-780 , sets guidelines for minimal terminal-to-hole clearance. IPC states that too small a clearance, as seen in Figure 6, can result in lack of solder "wicking", while too much clearance may also result in lack of solder "wicking" due to solder drainback. Lack of wicking can result in void formation, insufficient fillets, or a skipped topside fillet (three-sided solder joint). Furthermore, lack of clearance may also interfere with the fluxing action, thus further impeding wetting and intermetallic formation. Misalignment can also cause preferential damage and premature damage initiation in the weakest sections of the solder joint.
Low terminal height, displayed in Figure 7, can result in an inadequate solder joint, with the crosssectional area of the solder/terminal interface greatly reduced. Due to the nature of the wave soldering process, the solder will sometimes "fill in" the missing volume due to the low terminal height, resulting in a joint which will pass visual inspection, but may be close to experiencing an electrical open. Low terminal height can also lead to a change in the path of highest shear deformation, which may reduce the solder joints' resistance to periodic hygro-thermo-mechanical stresses. Terminal height that is higher than design specifications is rarely a problem unless the top of the terminal impedes or interferes with other parts of the electronic package.
Wettability is the affinity of the liquid solder for the surfaces of the terminal or pad, and is dependent upon solder temperature and composition, terminal and pad surface preparation, flux properties, application of flux, and the amount of preheat. The greater the wettability, the greater the tendency for the production of an optimum solder joint. Non-wetting, or poor wettability, can be due to poor fluxing, chemical contamination of the solder bath, inadequate preheat or solder bath temperature, oxide formation on the surface, or other imperfections and impurities present in the soldering process .
Intermetallic formation is a natural consequence of the reaction between the terminal, composed of copper, brass, or other electronic connector material, and the liquid solder, often an alloy of Pb-Sn. If the solder successfully wets the surface of the terminal, some amount of intermetallic phase will form at the interface, even though sometimes it is too thin to be visible under optical microscopy. The selection of the proper connector material can be critical. For example, brass, a common connector material, does not form a good intermetallic with Pb-Sn solder. It must often be plated with tin in order to ensure sufficient intermetallic formation. The reliability of solder joints can be greatly affected by the formation of intermetallic compounds because of their inherently brittle nature and thermal mismatch with the solder and the terminal. Previous studies have shown that while intermetallic formation is critical to formation of a strong interface, excessive intermetallic formation (primarily a function of the solder temperature and the cooling rate) can lead to a drop in the solder joint strength .
Crack propagation at the solder/terminal interface is identifiable by visual inspection or cross-sectioning (Figure 8) and can sometimes be an indication of poor wettability, inadequate intermetallic formation, or excessive intermetallic formation. Proper failure analysis requires an examination of the interface at much higher magnifications before the underlying failure mechanism can be determined. An example of this can be seen in the solder joints displayed in Figures 9a through 9c. All three solder joints were subjected to thermal cycling until an electrical open was detected. Crack propagation near the solder/terminal interface was observed upon optical examination of the cross-section of each of the solder joints. Using electron microscopy, at a higher magnification of 2500x, Figure 9a shows complete separation of the solder from the terminal. The lack of any solder or intermetallic on the terminal surface suggests a wettability problem. In addition, the small grain size in the solder adjacent to the separation implies that this area experienced negligible amounts of cyclic loading before separation. In Figure 9b, crack propagation can be seen to occur between the intermetallic phase and the solder. This does not imply poor wettability, but instead could be either a result of excessive intermetallic formation, or could indicate that the highest stressed region has moved close the interface due to faulty fillet formation (Figure 9c). Wettability can also be a problem at the solder/copper bond pad interface, as seen in Figure 10. If wetting is poor on the PWB bond pad, a fatigue crack can initiate at the same site as in a nominal joint, but propagate along the solder/pad interface, instead of taking a 45 degree path through the bulk of the solder.
An optimum amount of solder in the top-side and bottom-side fillets is critical in creating a durable single-sided joint. Insufficient solder fillets, such as shown in Figure 11, weaken the solder joint due to a reduction in the solder area. In addition, the change in the solder fillet shape leads to a change in the path of maximum shear strain in a solder joint due to differential thermal expansion. This can lead to a change in the failure initiation site and will alter the crack propagation path. The initiation site will shift from the root of the bottom fillet, near edge of the copper bond pad, to an area near the terminal/solder interface. The fatigue crack will then propagate along the solder/terminal interface, an area greatly reduced in cross-sectional area and strength in comparison to the nominal 45 degree bulk solder fatigue path.
Insufficient solder fillets are an indication of a non-optimized soldering process. Their formation is dependent upon a variety of interacting factors such as the assembly design, the assembly process, the shape of the solder wave, temperature of the solder bath, and wettability. If there is a large terminal-tohole clearance, solder drainback may occur. If the terminal-to-hole clearance is too small, there may not be enough clearance to allow the solder to flow down the hole and form a component-side fillet. If the amount of preheat is not adequate during the wave soldering process, the circuit board and the components will not reach optimum temperature and the solder will not rise properly. If the solderability is poor or the activity of the flux is not adequate, solder will not readily wet the terminal or pad surfaces.
Soldering process problems can lead to missing solder on one or more sides of the terminal, as seen in Figures 12. Two- and three-sided solder joints are of particular interest because they are easily observable indicators (using non-destructive visual inspection) of a manufacturing process that is not "optimal" for the design and is thus producing parts that can be intrinsically weak. A complete lack of solder can lead to degradation of the durability of the solder interconnect. Probable causes of incomplete solder formation include lack of plating on terminal or pad, oxides or other contamination of the terminal or pad surfaces, poor terminal seating or alignment, inadequate terminal fluxing, outgassing, a poorly controlled solder process, and inadequate slot dimensions and shape.
The chemical composition of 63Sn/37Pb solder is well defined, with maximum allowable contamination limits defined by the ANSI standard J-STD-001B  (Table 1). When the Sn/Pb ratio fluctuates or contamination limits are exceeded, the solder can suffer diminished wetting performance and/or excessive amounts of dross. The effects of poor wetting have already been discussed in Section 3.5. Dross refers to oxides and other contaminants that form on the surface of the molten solder bath. One indication of excessive dross includes the formation of icicles, as shown in Figure 13. Icicles pose no immediate reliability problems, assuming the additional height does not interfere with other surfaces . A more significant outcome of excess dross is plugged wave nozzles, which can result in an increase in the number of two- and three-sided joints.
Failure in solder joints can be due to a complex relationship between operating environment, system design, board material, solder joint strength, and the presence of failure accelerators. Assessment of the root cause(s) of failure necessitates the identification of the predominant failure mode, its location, and the underlying mechanism which precipitated failure. Placing this dissimilar information in the same grouping scheme renders preliminary failure characterization ineffectual. Using a physics-of-failure (PoF) approach can determine the series of events that could lead to unacceptable rates of electronic assembly failure.
PoF is grounded in complete understanding and appraisal of operational loads, environmental conditions, product geometry and materials, and possible defects. Use of this information allows the designer to determine the stresses that arise throughout the product life cycle, including manufacturing, handling, storage, and operation. A reliability assessment and sensitivity analysis can then determine the most likely failure mechanism, the time-to-failure for that mechanism, and its sensitivity to various defects. PoF can also evaluate and optimize accelerated testing conditions, which are used to confirm reliability predictions. PoF is most effective when used during the design process, but it is also capable of determining the cause of low reliability once failure has occurred. A complete failure analysis of solder joints depends upon performing visual inspections, characterization of solder joint cross-sections, accelerated testing, and lifetime modeling.
Visual inspection provides immediate information on the condition of the solder joint. Initial visual inspection will concern itself with identifying solder mask defects, excess solder (such as solder balls), surface irregularities (such as pinholes), poor wetting, and missing or insufficient solder fillets. If the solder joints have been in the field or subjected to accelerated testing, visually inspecting the fatigue crack propagation path can identify poor intermetallic formation. For proper failure analysis, visual inspection should be conducted at magnifications up to 25x using a stereoscope. Only after a thorough visual inspection has been completed and catalogued is it appropriate to cross-section the solder joints for further analysis. All solder joints should be mounted at room temperature in a rigid epoxy to prevent any additional damage from occurring during cross-sectioning. Cross-sections should be finely polished, since important defect information may not be apparent after a rough grind or cut. Inspection of the cross-section, using optical or electron microscopy, allows for the observation of interior defects, including internal voids, poor terminal seating, insufficient fillets on the component side, and poor wettability or insufficient intermetallic formation along the terminal surface. Use of energy dispersive spectroscopy (EDS) can provide evidence of contamination in the solder exceeding ANSI J-STD-001B guidelines. Fluctuations in the quality of solder process are expected, and observation of these defects does not necessarily indicate a root cause of accelerated failure. Visual inspection and cross-sectioning provide important details on the occurrence, size, and shape of defects present, which can then be used to estimate lifetime distribution.
The use of accelerated testing and lifetime modeling allows for an assessment of the influence of defects on the durability of solder joints in single-sided boards. Accelerated testing is used to precipitate in a timely manner failures that would normally occur during operation. The relevance of the accelerated test depends upon an accurate evaluation of the ambient environment, including temperature range, humidity levels, and possible exposure to pollutant gases. Errors in the estimation of the environmental conditions can result in a non-optimized accelerated test, leading to false positives or failure modes not found in field use. A standard test is to thermally cycle the PWBs, with the temperatures based upon operating conditions and the accelerated failure rate dependent upon the frequency of the thermal cycle. The assemblies, such as single-sided PWBs with insertion-mount devices, are cycled until they have exceeded the expected operational lifetime or a defined failure occurs (e.g., an electrical open). The specific solder joint that exhibited electrical failure is then visually inspected and cross-sectioned in order to observe solder joint quality. If the failure mechanisms have been correctly assessed, the singlesided assemblies that fail early will exhibit defects similar to those found in assemblies that suffered premature failure in the field. In addition, assemblies with extended lifetimes during accelerated testing will tend to have solder joints that display the characteristics of an optimum single-sided solder joint.
Lifetime modeling can be conducted to investigate the effect of various failure accelerators on solder joint durability. The methodology adopted by the CALCE Consortium to predict damage in solder interconnects under temperature cycling has been described previously [7-9]. A thermal loading profile is applied to the three-dimensional finite element model. The energy metrics from the resulting stressstrain hysteresis loop is used in an energy-partitioning model to create lifetime predictions. This analysis separates structural responses from material behavior, which allows for a wide range of applicability across various parameters, such as terminal materials and geometries, substrate materials, solder joint design, etc. As an example, a rectangular, single-sided, insertion-mount solder joint with complete wetting on all four sides was treated as a baseline nominal 3-D model. The effect of incomplete or missing solder fillets can be seen in Figure 14. Detailed stress and damage analysis indicates that a three-sided solder joint, a commonly encountered manufacturing flaw, will have 60% of the expected lifetime of the four-sided nominal solder joint. A two-sided solder joint was found to be only one-third as durable as the four-sided case.
The effect of misregistration and the accompanying starved solder fillet is displayed in Figure 15. Poor wetting, defined as a lack of interfacial strength between the solder and terminal surface, results in premature delamination and a corresponding increase in the stresses experienced by the remaining portions of the solder joint. Analysis of the situation for poor wetting on two sides of a terminal shows that the joint will last approximately half as long as the baseline case (Figure 16).
Low cost insertion-mount substrates, such as single-sided CEM boards, play an important role in electronic packaging and assembly. Their low cost and compatibility with standard soldering processes are important for many applications. However, in order to obtain and maintain high reliability, the manufacturer and the end user must take into consideration the effect of variations in stresses from assembly, processing, and usage, especially on the solder joint.
Poorly controlled assembly and non-optimized solder processes will lead to the introduction of a variety of failure accelerators into the solder joints, such as large voids, poor terminal seating, insufficient solder fillets, poor wettability, insufficient intermetallic formation, missing solder fillets (solder and component-side), and excessive solder contamination. These defects can increase a single-sided solder joint’s susceptibility to stress and decrease the durability of the solder joint.
In order to create and maintain an optimized soldering process, all phases of the single-sided PWB manufacturing process (assembly, flux application, preheat, wave soldering, etc.) should be continuously monitored. In addition, random sampling of the product must be rigorous and based upon statistical analysis. It also should include characterization and accelerated testing designed to assess potential problems in actual operation.
Characterization of defects such as voids or poor intermetallic formation at pad or terminal may be accomplished only upon cross-sectioning. Therefore, frequent periodic visual examinations of the solder joints alone, although necessary, are not sufficient. Cross-sections of new and accelerated tested joints must also be made to allow one to grasp the whole picture so that appropriate causes for premature failures can be identified and solutions to the observed modes of failures correctly prescribed.
The selection of low-cost insertion-mount substrates can provide a competitive advantage. However, to ensure a highly reliable assembly, a physics-of-failure approach should be instituted during the design process and there should be a system for continual supplier assessment.
The authors would like to acknowledge the finite element studies designed by K. Darbha, K. Upadhyayula, and J. Song. The authors would also like to acknowledge the finite element computation performed by ACE Engineering, West Lafayette, IN.
Michael Pecht is a Professor and Director of the CALCE Electronic Products and Systems Center at the University of Maryland. The CALCE EPRC is sponsored by over 40 organizations and conducts reliability research to support the development of competitive electronic products in a timely manner. Dr. Pecht has a B.S. in Acoustics, an M.S. in Electrical Engineering, and an M.S. and Ph.D. in Engineering Mechanics from the University of Wisconsin. He is a Professional Engineer, an IEEE Fellow, an ASME Fellow, and a Westinghouse Fellow. He is the Chief Editor of the IEEE Transactions on Reliability; an Associate Editor for the SAE Reliability, Maintainability and Supportability Journal; an Associate Editor on the International Microelectronics Journal; and on the advisory board of the IEEE Spectrum and the Journal of Electronics Manufacturing. He serves on the board of advisors for various companies and consults for the U.S. government, providing expertise in strategic planning in the area of electronic packaging.
Craig Hillman is a faculty member within the CALCE Electronic Products and Systems Center at the University of Maryland. Dr. Hillman received a B.S. in Metallurgical Engineering and Materials Science and in Engineering and Public Policy from Carnegie Mellon University in Pittsburgh, PA. He then received his Ph.D. in Materials at the University of California-Santa Barbara investigating the effect of architecture and stresses on the strength and reliability of layered materials. Before accepting the current position at CALCE, Dr. Hillman completed a research fellowship at Cambridge University in Cambridge, England.
Keith Rogers is a research engineer at the University of Maryland’s CALCE Electronic Products and Systems Center. His part-time work as an undergraduate in the CALCE EPRC was converted to fulltime in 1994 after obtaining a B.S. degree in mechanical engineering from the University of Maryland. Mr. Rogers won first place among over 100 contestants in his initial poster presentation at the IEEE Conference at Georgia Tech where he represented CALCE. He has published a paper entitled "Applications of the Environmental Scanning Electron Microscope" in the July 1995 issue of Advanced Materials & Processes, and co-authored many others. His expertise lies in the operation of equipment used in electronic failure analyses and is an instructor of most of the machines. He is currently pursuing a M.S. degree in mechanical engineering at the University of Maryland.
Abhijit Dasgupta received the Ph.D. degree in theoretical and applied mechanics from the University of Illinois, Urbana. He is a Professor and Researcher with the CALCE Electronics Products and Systems Consortium at the University of Maryland. He conducts research in the area of micromechanical modeling of constitutive and damage behavior of heterogeneous materials and structures, with particular emphasis on fatigue and creep interactions. His research also includes associated stress analysis techniques under combined thermomechanical loading, formulating physics-of-failure models to evolve guidelines for design, validation testing, screening, and derating of reliable electronic packages.
Rich Dusek is an Engineering Group Manager at the North American Operations of General Motors
Brian Lorence is an Engineering Group Manager at General Motors Truck Group.
Solder fatigue is the degradation of solder under cyclic loading. During temperature cycling, stresses are generated in the solder due to coefficients of thermal expansion (CTE) mismatches between the printed circuit board (PCB) and the components. Extensive work has been completed to characterize the behavior of various solder alloys and develop predictive solder fatigue damage models using Physics-of-Failure (PoF) approaches.
Solder fatigue is the degradation of solder under cycling loading. This loading can come in several forms (i.e. drop/shock, vibration, temperature cycling) however the majority of solder fatigue in electronics is thermomechanical driven due to temperature cycling. During temperature cycling, stresses are generated in the solder due to coefficient of thermal expansion (CTE) mismatches between the PCB and component. This causes the solder joints to experience non-recoverable deformation that accumulates and leads to degradation and eventual fracture. Much work has been done to characterize the behavior of various solder alloys and develop predictive solder fatigue damage models using a Physics-of-Failure (PoF) approach.