Understanding plated through via failures

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Plated through vias (PTV), also known as plated through holes (PTHs), were revolutionary when they were first introduced in the late 1950’s/early 1960’s. The concept of plated holes to route electrical signals was the genesis for the first ‘3D’ revolution in electronics. No longer limited to the two-dimensional plane of a single layer paved the pathway for double sided, multilayer surface mount technology. This is still state of the art even today.

Of course, the original concept of a plated through via, which is a hole drilled through the entire thickness of the printed board and then plated along the wall of hole, has been expanded upon since its original introduction 50 years ago. There are now buried vias (in which the hole is only drilled through part of the printed board thickness), buried microvias (the hole is only drilled through one layer or two layers and ends at a capture pad), blind microvias (the microvia starts at the surface of the printed board) and filled vias/ microvias (the hole is filled with epoxy or plated copper).

However, from a reliability standpoint, the area of greatest interest is still the original PTV (note: I differentiate PTVs from PTHs. PTHs, from my humble perspective, are holes that have pins soldered to the barrel). PTVs are a concern because micro vias and filled vias (especially those filled with copper plating) are extremely robust. Robust to the point that it is not worth the effort to have too much of a discussion.

When talking about PTVs and failure, the primary mechanism of concern is barrel fatigue. Barrel fatigue is the circumferential cracking of the copper plating that forms the PTV wall. The fatigue occurs because of the differential expansion of copper plating (~17 ppm/˚C) and the printed board (between 45 to 75 ppm/˚C).

Avoiding barrel fatigue is a big deal because barrel fatigue, like many degradation mechanisms, tends to have a latency period (it waits before it rears its ugly head). And the last thing you (customer/ supplier, CEO/engineer) is a huge population of defective product that’s just going to get worse. So, how to avoid PTV issues? It all comes down to three key drivers: PTV architecture (height/diameter), PCB material selection (modulus/thermal expansion), and plating (thickness/material).

The PTV architecture is typically the driver that seems to get the most attention. Larger PCBs (and therefore longer PTVs) or smaller PTVs are ‘bad’, with numerous companies ‘discovering’ barrel fatigue once the via diameter goes from 300 microns (12 mil) to 250 microns (10 mil) or from 250 microns (10 mil) to 200 microns (8 mil).

But despite the attention, PTV architecture actually has the least influence, especially given the realistic limitations in regards to what you can change. For example, moving from 250 microns to 300 microns diameter on a 3 mm board, 50˚C temp cycle, will result in approximately 20% improvement. That’s nice, but it doesn’t really give you the kind of margin that makes the problem go away completely. And for most designers, going from 250 micron diameter PTV to 350 or even 400 micron diameter PTV is not realistic.

But, while changing PTV architecture will not theoretically change barrel fatigue onset by much, it can have an outsized influence on the occurrence of process defects. The best experts in electronic design and manufacturing have always realized that PCB and SMT manufacturing processes have cliffs. Cross over and risk an exponential increase in defects into your product. The best example of this is PTV diameter. As seen in Figure 1, the capability of PCB industry to reduce PTV diameter has for the most part stagnated. Your company may want 250 micron diameter, but that may put your supply chain into dangerous territory.

Where PTV architecture can have a limited influence, especially given the limitations in changing PCB height and PTV diameter, laminate/prepreg material properties can have a significant effect on PTV reliability without the need to change any aspect of the PCB design. The most important material properties are out of plane (Z direction) coefficient of thermal expansion (CTE) and out of plane elastic modulus. When selecting the right material properties, it is important to understand what is available from the supply chain and how the supply chain communicates those material properties.

For example, as Figure 2 shows, there is a wide, but limited range of out of plane CTE values (for those looking for percent (%) expansion between 50-260˚C, the equivalent range is 1.4% to 4.8%). However, out of plane modulus values are often never provided by laminate/prepreg suppliers.

And these CTE values listed above are not the end of the story. This is because laminates and prepregs come in a variety of glass styles. Starting with 7628, which is comprised of 36 volume percent (vol%) of glass fiber, all the way to 106, which has as little as 16 vol% of glass fiber. Different glass style can dramatically change material properties, but all datasheet properties are only for 7628 glass style. This is a big deal, especially since high technology PCBs that are the most at risk for PTV failures are often never fabricated with 7628 laminate. As seen in Figure 3, out of plane CTE can end up being almost 50% higher than the values stated on the datasheet.

With the advent of Pb-free manufacturing processes (quick side note: can you believe it has been over seven years since the original RoHS legislation went into effect?), other PCB material properties have also become increasingly important. These include glass transition temperature (Tg), time to delamination (T260, T280, T288, T300), and temperature of decomposition (Td). While T288, the most popular time to delamination temperature, and Td supposedly capture different behaviors, there have been a number of experiments that have demonstrated a strong correlation. That is, when a material is about to decompose, it will also start to delaminate (and vice versa).

The last, and possibly the most important, driver for PTV reliability is the plating. The most interesting aspect of plating is the classic engineering conflict: Better properties (greater thickness, higher plating strength, greater elongation) typically require longer time in the plating bath, but longer time in the plating bath reduces throughput, making PCBs more expensive to fabricate. PCB fabricators, low margin business, try to balance these conflicting requirements, with the key parameters being thickness, strength, and elongation (ductility).

Thickness has always been a major focus, especially for high-reliability industries, because it is the easiest plating parameter for OEMs to identify. However, with new fast plating formulations, it has become less of an issue than with previous generations of PCB designs. What is more interesting is how the best PCB shops will tweak plating strength and elongation to meet test requirements of high reliability customers. The ‘tweaking’ has been so successful that some PCB shops can show similar times to failure for a PTV with an aspect ratio of 5 (1.5 mm thick PCB and 300 micron diameter PTV) and an aspect ratio of 13 (3.8 mm thick PCB and 300 micron diameter PTV).

To wrap it up, and really there is much more to talk about, the base knowledge and understanding of PTV failure is robust, with decades of testing and simulation and the use of reliability physics to predict PTV lifetime being a best practice. Do the right things up front and PTVs can be your best friend.

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Craig Hillman is CEO and Managing Member for DfR Solutions. Dr. Hillman’s specialties include best practices in Design for Reliability (DfR), Pb-Free strategies for transitioning to Pb-free, supplier qualification (commodity and engineered products), passive component technology (capacitors, resistors, etc.), and printed board failure mechanisms. Dr. Hillman has over 40 Publications and has presented on a wide variety of reliability issues to over 250 companies and organizations.