Join us at the ASME Interpack 2019 on October 7th-9th, 2019 in Anaheim, California. Gil Sharon, Senior Application Engineer at ANSYS-DfR Solutions, will be presenting "Automated Method Using Finite Element Analysis to Identify Plated Through Holes and Microvia Stacks at Failure Risk in Complex PCB Designs" on Wednesday, Oct. 9th at 10:45 am as part of the technical track 8-1: ECU Level Reliability.
Since the introduction of plated through holes and microvias into the electronics industry, the reliability and manufacturability of these interconnects have been of great concern to the board designers, specifically in automotive and semiconductor industries. The failure of these structures is one of the main causes of an open circuit in printed circuit boards (PCBs). Typically, single and staggered microvias are not the cause of the failures, therefore, only stacked microvias and plated through holes (PTHs) are considered and analyzed in this study. This study includes broad parametric studies, using the finite element method (FEM), to investigate the effect of different geometrical parameters on the reliability and manufacturability of the stacked microvias and plated through holes. A fully automated methodology is developed to 1) analyze complex PCB designs with thousands of microvias and plated through holes, 2) identify and mark configurations susceptible to failure, and 3) build and run finite element simulations on the marked configurations. In doing so, the PCB drill files are first parsed, and the configurations are binned into three main categories; stacked, staggered and PTH configurations. Then using the related nearest-neighbor algorithms and based on the parametric study results, the configurations prone to failure are identified. Finally, finite element models are generated and simulated under thermal loading for the identified configurations. The simulations results are post processed for both reliability (fatigue life prediction under thermal cyclic loading over PCB service life) and manufacturability (overstress due to thermal shock during solder reflow). The modeling results and predictions correlate well to the experimental results available in the literature.
About the event:
The International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems (InterPACK) is the flagship conference of the Electronics and Photonics Packaging Division (EPPD), in technical co-operation with the Japanese Society of Mechanical Engineering (JSME).
October 7th-9th, 2019
777 W Convention Way
Anaheim, CA 92802