Uprating of Ceramic Capacitors

By Craig Hillman, PhD

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Ceramic capacitors are chip components that consist of alternating layers of dielectric material and metal conductors (typically AgPd or Ni alloys). Ceramic capacitors are primarily used to filter high-frequency electrical signals and because of their extremely high capacitance-to-volume (C/V) values.

The critical functional parameters of ceramic capacitors are defined as capacitance (C), equivalent series resistance (ESR), insulation resistance (IR), and dissipation factor (DF). These parameters are interrelated through the following schematic

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where Rp is insulation resistance and Rs is ESR. As with electrolytic capacitors, insulation resistance, and therefore leakage current, is driven primarily by the behavior of the dielectric. Insulation resistance is relatively high for ceramic capacitors, with resulting negligible leakage current. ESR is primarily driven by the behavior of the electrolyte. Physically, impedance (Z) is a summation of all the resistances throughout the capacitor, including resistances due to packaging. Electrically, Z is the summation of ESR and either the capacitive reactance (XC), at low frequency, or the inductance (LESL), at high frequency (see Error! Reference source not found.). Dissipation factor is the ratio of ESR over XC. Therefore, a low ESR tends to give a low impedance and a low dissipation factor.

Functional Parameters (Specified in Datasheet)

An example of the variation in functional parameters that can be provided in manufacturers’ datasheets is listed below

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Capacitance vs. Temperature

Class II dielectrics are well known to have capacitance values that can be very sensitive to temperature (see Figure 3). Since Y5V is an EIA performance specification and does not define a particular mixture, the capacitance behavior over the given temperature range can vary extensively while still staying within the requirements of +22% / -82%. Some of the capacitance behaviors displayed in Figure 1 through Figure 3 suggest that Y5V capacitors could drop below -82% when temperatures reach -40C.

However, once any significant bias is applied to these capacitors, the actual capacitance drops precipitously and the capacitance change over temperature is minimized (see Figure 4).

Insulation Resistance vs. Temperature

As a general statement, insulation resistance logarithmically decreases with increasing temperature (see Figure 5 and Figure 6). There is some variation on how manufacturers specify insulation resistance.

TDK and MuRata do not state a specified temperature for their insulation resistance value. Therefore, the value provided in their datasheets can be interpreted that the manufacturer guarantees this maximum leakage current over the specified temperature range. This may also explain why their insulation resistance values are lower than Epcos, which clearly indicates an insulation resistance value at 20C, and Taiyo Yuden, which indicates that all testing is performed under “standard test conditions”.

While Epcos and Taiyo Yuden’s failure to provide insulation resistance over the specified temperature range does provide some risk, review of test results from the literature seem to indicate that a decrease in insulation resistance greater than one order of magnitude from room temperature to 85C is unlikely. This would still provide 100 M­ of resistance, which should be sufficient for most applications. In addition, EIA specifications require that the RxC product exceed 1000 Ohm-Farad (often expressed as 1000 Megohm-Microfarad) at 25°C, and 100 Ohm-Farad at 125°C, (10% of the values of Table G-1 (see Figure 7)).

ESR vs. Temperature

Manufacturers of ceramic capacitors do not provide an ESR value in their datasheet nor do they specify the maximum variation in ESR over the specified temperature range. While this could be somewhat discerning, the ESR values of ceramic capacitors are typically very low (ceramic capacitors are often selected in applications requiring low ESR).

However, the behavior of the dissipation factor, which is directly influenced by ESR, as a function of temperature is provided.

Dissipation Factor vs. Temperature

The complexity of the ceramic microstructure and the resultant multiple Curie Points of the aggregate polycrystalline components in any given formulation do not permit a clear prediction of DF behavior with temperature, other than the fact that DF is inversely proportional to temperature. At elevated temperatures below the Curie Point, DF is relatively stable. However, at cold temperatures, especially below 0C, the dissipation factor can increase by a factor of 5 above the manufacturer’s specifications (see Figure 8 and Figure 9).

However, as with capacitance, this significant increase is minimized once any significant bias is applied.

Functional Parameters (Not Specified in Datasheet)

All functional parameters are specified within the manufacturer’s datasheet

Electrical Overstress1 (Robustness)

Ceramic capacitors can experience electrical overstress type failure mechanisms through the application of excessive voltage or excessive current.

Voltage Rating

The capacitor manufacturers do not provide any indication on the variation on breakdown strength as a function of temperature. However, two activities by the manufacturer tend to limit any concern about change in the voltage rating. First, a standard screen in the industry is to apply a 2X rated voltage. Second, the industry standard life tests require testing at 2X rated voltage and maximum rated temperature for 1000 to 2000 hours. Therefore, the design of the capacitor has been demonstrated to be robust to dielectric breakdown to the extremes of the manufacturer’s ratings.

Current or Power Rating

Ceramic capacitors can experience a temperature rise due to the application of elevated levels current or power. Capacitor manufacturers often provide recommended limits on current or power to prevent temperature rises greater than 20C or temperatures greater than the specified maximum temperature. Review of existing datasheets found minimal information on this need for derating outside of MuRata and Syfer (see Figure 10 and Figure 11).

Wearout Behavior

The wearout behavior of ceramic capacitors, degradation in insulation resistance due to migration of vacancies, is well known and is captured by the industry standard wearout model

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where t is time, V is voltage, T is temperature (K), n is a constant (1.5 to 7), Ea is an activation energy (1.3 to 1.5) and KB is Boltzman's constant (8.62 x 10-5 eV/K). Wearout of ceramic capacitors has typically not been an issue, but increasing miniaturization has resulted in capacitor materials and architectures that could wearout within 10 years (see Figure 12). This behavior is dependent upon the capacitance/volume ratio (C/V).

The C/V ratio of concern is approximately greater than 5 to 10 uF/mm3. This equates to roughly 2 to 3 microns of dielectric thickness. Unfortunately, most customers of ceramic capacitors often are unaware of the component thickness, which prevents a calculation of C/V. Therefore, an alternate approach is to list capacitance levels of concern for a given case size and dielectric material. One example is X5R in an 0805 case size. Reliability assessments should be performed once capacitance levels are 10 uF or higher.

Capacitors are also known to ‘age’, which induces a drop in capacitance over time (see Figure 13). Y5V dielectric ages approximately 5-7% per decade. Quantitative information about the change in aging rate as a function of temperature were not obtained, but it is believed to be relatively temperature independent, with the driving force for aging reducing with increasing temperatures.


The primary risk in using ceramic capacitors beyond their rated temperatures is the potential for insufficient reliability of ceramic capacitors with extended value (high C/V ratios).


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