Power supply is the core of electronic equipment. But as crucial as it is, designing a power supply can be difficult due to an indirect feedback loop within design teams, especially when it comes to thermal solutions. It is often more difficult to know what the temperature should be as opposed to what the temperature will be.
When our customers approach us about battery reliability, the most pressing question is always, “How do we prevent catastrophic battery failures?” While the rate of field failures is statistically low at only 1 to 10 ppm, the impact of battery failures has often been severe in recent years. Higher energy densities, and the use of lithium ion batteries closer to the human body are to blame for the severity of impact.
Underfill is thermoset epoxies traditionally used in flip chip applications to reduce thermal stresses solder bumps experience due to coefficient of thermal expansion mismatch between a die and the organic substrate. Today, underfills are available in a variety of formulations and are widely used for board level reliability of ball grid array components by reducing thermal and mechanical loads under harsh use environments. Careful consideration to the underfill material properties and intended use environments must be made to assess the relative reliability improvements underfills offer.
Here at DfR Solutions, we perform hundreds of design review projects a year. Sometimes companies come to us when they are considering a new electronic product and have only the initial designs. In other instances, companies approach us only after their product has already been configured, requesting a review of the final design before moving forward to the manufacturing stage. Ideally for the client, they are in the former group, partnering with us as early in design process as possible. It’s much more efficient (time- and cost-sensitive) to gather all available information and thoroughly check for potential failures of a design before nailing parts down, rather than to complete an assembly only to discover it doesn’t function properly in its use case scenarios.
Working closely with our clients, we receive constant feedback about current challenges facing our industry. This allows us to tailor Sherlock updates to address rapidly developing landscapes as we continuously strive to improve Sherlock to make reliability predictions more accurate and more appropriate to Sherlock users’ needs.
As part of our mission to make Sherlock the most dependable and extensive reliability analysis tool available, we are rolling out an update to our flagship software. The two newest features in Sherlock addresses two key challenges: modeling non-standard BGA layouts and predicting the fatigue life of assemblies utilizing Insulated Metal Substrates (IMS).
In a previous DfR Solutions insight titled Best Practices in Test Plan Preparation, we discussed some of the most important techniques and philosophies when preparing to develop a testing plan for electronic products. What makes those techniques so powerful is that they are ubiquitous: with any design, reviewing the bill of materials, identifying use environments and assessing failure history are both applicable and crucial.
However, what that article did not discuss is that there are considerations that need to be applied in very specific ways. The following are strategies for test plan development that are dependent on specific use cases, parameters, goals, configurations and limitations. While they are just as powerful as our Best Practices, they require a thorough understanding of your product and a clear and agreed-upon set of goals throughout the supply chain.
Product test plans are critical to the success of a new product or technology. Preparing a viable test plan involves several steps to properly identify the requirements for the tests. While many test parameters will vary from product to product, there are elements of the methodology for a test plan approach that remain consistent. These include the necessity for a BOM review to determine part limitations, assessing the field environmental conditions so they can be properly mapped to the tests implemented, and the impact of failure history, should it exist. The objective is to develop a test plan that does not stress the assembly to a level where a failure might not be experienced in the field.
As the smartphone market has stagnated, semiconductor manufacturers have started to pivot their focus to automotive electronics to find the next large volume growth opportunity. This adjustment is for good reason: while smartphone volumes have not changed in over three years, automotive electronics will be the fastest growing market for integrated circuits until at least 2021.
To be successful in the competitive landscape that is automotive electronics, semiconductor manufacturers must account for differences in how automotive OEMs and their suppliers qualify integrated circuits compared to consumer products. While the differences are numerous, a key factor is the critical importance of board level reliability testing.
For semiconductor manufacturers entering the automotive environment, the lack of universal qualifications standards often leads to inconsistent reliability expectations. To be successful in the competitive landscape, semiconductor manufacturers must account for differences in how automotive OEMs and their suppliers qualify integrated circuits compared to consumer products. A key factor in the qualification process is the critical importance of board level reliability testing. Given the varied requirements and absence of mutually agreed standards, semiconductor manufacturers often struggle to develop a relevant and successful board level reliability test plan.
The movement to Pb-free soldering will result in solder joints that are significantly stiffer than those made of SnPb. This paper presents the results from the first phase of a two-part study to understand and compare the isothermal mechanical fatigue behavior of tin-silver-copper (SnAgCu) solder to that of tin-lead (SnPb) solder. A combination of experiments and finite element analysis was used to compare and predict the durability of SnPb and SnAgCu surface mount solder joints. The experiments were composed of cyclic four-point bend tests of printed wiring board coupons populated with 2512 sized resistors at 5 and 10 Hz. This configuration was chosen so the test would reflect actual electronic products and still be rapidly modeled using finite element analysis (FEA). This frequency should be sufficiently high to minimize solder creep during the testing. The board level strains were verified with strain gauges and the solder joint failures were detected using a high-speed event detector. Tests were conducted at two board level strain values and then modeled in FEA to determine the strains and stresses developed in the solder joint. This information was then used to determine the appropriate cyclic fatigue relationship for both SnAgCu and SnPb solder. The results indicate that at high board level strains SnPb solder out performs SnAgCu solder. However, at lower board level strains the SnAgCu solder out performed SnPb. The second phase of the study involves bend testing at even lower board level strains to characterize the high cycle fatigue behaviors of the solders.
